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Visitor 8005773346
Visitor
5,333 Views
Registered: ‎08-20-2014

Vivado. Synthesis. ROM + DSP, registers absorbing.

Hi! I have next statements in my project:

 

if (rising_edge(CLK)) then

reg0 <= ROM(address);

reg1 <= reg0;

 

reg2 <= reg1;

mult_result <= reg2 * other_value;

end if;

 

I want to implement it this way: reg0, reg1 are absorbed to BRAM and reg2, mult_result are absorbed to DSP48E1.

But Vivado's synthesizer absorbs reg1, reg2 to DSP48E1 and reg0 - to BRAM, so after implementation it fails to meet timing.

What can I do to force absorbing by my way?

 

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3 Replies
Scholar muravin
Scholar
5,315 Views
Registered: ‎11-21-2013

Re: Vivado. Synthesis. ROM + DSP, registers absorbing.

The VIVADO realizes that it can absorb 3 registers as AREG/BREG=1, MREG=1and PREG =2 and the BRAM readout is unregistered.

 

Possible solutions:

1. Add another pipeline in between and make sure it is not absorbing it as AREG=2/BREG=2, if it does, add yet another pipeline.

2. Instantiate BRAM/DSP manually

 

Regards

Vlad

Vladislav Muravin
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Visitor 8005773346
Visitor
5,305 Views
Registered: ‎08-20-2014

Re: Vivado. Synthesis. ROM + DSP, registers absorbing.

Thanks, but I've found more elegant solution:

 

if (rising_edge(CLK)) then

reg0 <= ROM(address);

reg1 <= reg0;

 

reg2 <= reg;

mult_result <= reg2 * other_value;

end if;

 

reg <= reg1; -- with attribute "dont_touch" on "reg".

Adventurer
Adventurer
335 Views
Registered: ‎04-07-2014

Re: Vivado. Synthesis. ROM + DSP, registers absorbing.

Hi,

your solution works great. Thanks a lot.

 

Regards,

Sebastian

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