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Explorer
Explorer
430 Views
Registered: ‎07-10-2013

Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

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When instantiating in Verilog a RAMB36E2 primitive, which has a total of 54 input and output ports, but leaving ten unneeded outputs unconnected, Vivado 2018.3 Synthesis issues the warning "...instance "foo' of module 'RAMB36E2' requires 54 connections, but only 44 given...".  Note the use of "requires", which is incorrect.

It would seem that this misleading warning message would be better reworded as "...instance "foo' of module 'RAMB36E2' has 54 connections declared, but only 44 given...", or even better: "...instance "foo' of module 'RAMB36E2' has 40 input and 14 output connections declared, but only 4 output connections given...".

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Moderator
Moderator
271 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

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Hi @chsdkj,

Enhancement Request has been filed for this warning messag. Developers team will look into and may make necessary changes as per the requirement for upcoming Vivado versions. 

Regards,
hemangd

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4 Replies
Moderator
Moderator
411 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

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Hi @chsdkj,

Can you provide a testcase show i can regenerate this warning at my end and file an enhancement request with the development?

If yes, i will share the ezmove ftp link.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Explorer
Explorer
387 Views
Registered: ‎07-10-2013

Re: Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

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@hemangd,

Yes, I can.

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Moderator
Moderator
367 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

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Hi @chsdkj,

Ezmove ftp test package sent on your attached email id. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Moderator
Moderator
272 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis "Requires" Connection To Verilog Module Output Ports!

Jump to solution

Hi @chsdkj,

Enhancement Request has been filed for this warning messag. Developers team will look into and may make necessary changes as per the requirement for upcoming Vivado versions. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos