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Newbie jackwadden
Newbie
143 Views
Registered: ‎09-13-2018

Vivado Synthesis stuck in timing optimization after small, seemingly innocuous Verilog change

Hi Forum,

I found an always block in my code that looked like the following:

always @ ( * ) begin
  output_signal = output_signal;
  if((state == `STATE_4) && state_change_valid) begin
     output_signal = other_var >> 4;
  end else if((state == `STATE_5) && state_change_valid) begin
     output_signal = other_var >> 3;
  end
end

 This simulated and synthesized fine but had bad behavior in hardware due to poor programming. I recoded the block into two blocks like the following:

//
reg [7:0] regd_output_signal;
always @(posedge clk) begin
    if(rst) begin
regd_output_signal <= 'h0;
end else begin
regd_output_signal <= output_signal;
end end always @ ( * ) begin output_signal = regd_output_signal; if((state == `STATE_4) && state_change_valid) begin output_signal = other_var >> 4; end else if((state == `STATE_5) && state_change_valid) begin output_signal = other_var >> 3; end end

 

Now synthesis Timing Optimization takes over an hour (where previously it took a few minutes) and synthesis for the entire design gets stuck for over 12 hours in Technology Mapping. If I remove these blocks, or change the code back, full synthesis takes about 2.5 hrs and progresses normally.

I have no idea how to properly debug this. I have the clock at a fairly high period. There aren't any weird timing errors or timing loops. Is there some issue with my Verilog? Any suggestions for what could be going wrong?

I'm running Vivado 2018.2 using Amazon F1 AMI 1.5.0 developer instances.

Thanks,

-Jack

 

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3 Replies
Moderator
Moderator
120 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis stuck in timing optimization after small, seemingly innocuous Verilog change

Hi @jackwadden,

>>Now synthesis Timing Optimization takes over an hour (where previously it took a few minutes) and synthesis for the entire design gets stuck for over 12 hours in Technology Mapping.

1. So, now synthesis is stuck with timing optimization phase or technology mapping? And your title says: Vivado Synthesis stuck in timing optimization after small

- If it is stuck with timing optimization then try applying flow_runtimeoptimized strategy 

and then check with disabling XDC files for synthesis. 

Check if this suggestions help.

2. Which Vivado version are you using?

if above suggestion does not help, then provide your testcase to reproduce this runtime issue. 

 

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
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Newbie jackwadden
Newbie
116 Views
Registered: ‎09-13-2018

Re: Vivado Synthesis stuck in timing optimization after small, seemingly innocuous Verilog change

Timing optimization time is greatly increased, but it eventually passes. The whole design gets stuck in technology mapping (or at least takes 12+ hours).

I'm using Vivado 2018.2 as mentioned.

-Jack

 

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Moderator
Moderator
101 Views
Registered: ‎03-16-2017

Re: Vivado Synthesis stuck in timing optimization after small, seemingly innocuous Verilog change

Hi @jackwadden,

Can you try by diasabling XDC files for synthesis?

Also is it possible to provide full testcase (archived project) to reproduce this issue at my end?

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
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