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Participant
Participant
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Registered: ‎11-21-2007

Vivado Verilog: Missing Connection in Nested "Generated" Modules

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I have a Verilog design which is a TMR experiment which sends triplicated signals to a hierarchy of voter modules. The signals represent 36-bit products of triplicated 18x18-bit multipliers. I used generate statements to create multiple instances of modules. At the top level, I generate 6 6-bit majority voters (voter6bitmaj):

 

    genvar i;
    generate
        for (i = 0; i < 36; i = i + 6) begin
                voter6bitmaj voter6(prod1[i+5:i], prod2[i+5:i], prod3[i+5:i],
                                                voted[i+5:1], errsyn[i/6], voterr[i/6]);
        end
    endgenerate

 

Within the voter6bitmaj module, another generate statement creates 6 instances of a 1-bit majority voter (voter1bitmaj):

 

    genvar i;
    generate
        for (i = 0; i < 6; i = i + 1) begin
            voter1bitmaj voter1(vec1[i], vec2[i], vec3[i],
                                            voted[i], majerr[i], biterr[i]);
        end
    endgenerate

 

The attached voter6bitmaj_normal.jpg illustrates one of the 6 instantiated voter6bitmaj modules and, except for module names, looks the same as 5 of the 6 instantiated modules. Note that all of the maj1 outputs from the embedded voter1bitmaj modules are connected to the voted[5:0] output of the voter6bitmaj module as they should be.

 

However, as shown in voter6bitmaj_noxn.jpg, in one of the instantiated voter6bitmaj modules the last voter1bitmaj module has no maj1 output and only 5 signals are connected to voted[5:0].

 

Opening the voter1bitmaj module as shown in voter6bitmaj_noxn-exp.jpg, we can see that the maj output from the embedded voter module is not connected to the maj1 output as it should be.There is nothing in the generate statements to indicate that one of the modules should be instantiated any differently than all the others.

 

I should note that as I experimented with this code and changed some things, such as the number of instantiations or number of output signals, the symptoms of the problem changed somewhat but there was always one or more missing input or output signals. However, if I removed the generate statement from top level and instantiated the voter6bitmaj modules with constants,as below, the symptoms went away and the synthesized design was correct.

 

    voter6bitmaj voter6_0(prod1[5:0], prod2[5:0], prod3[5:0], voted[5:0], errsyn[0], voterr[0]);
    voter6bitmaj voter6_1(prod1[11:6], prod2[11:6], prod3[11:6], voted[11:6], errsyn[1], voterr[1]);

    // etc...

 

Is there a known problem with nesting generated modules in this way?

 

Thanks,

Ron Aikins

voter6bitmaj_normal.jpg
voter6bitmaj_noxn.jpg
voter6bitmaj_noxn-exp.jpg
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Highlighted
Scholar
Scholar
11,766 Views
Registered: ‎09-16-2009

@space_boy wrote:

I have a Verilog design which is a TMR experiment which sends triplicated signals to a hierarchy of voter modules. The signals represent 36-bit products of triplicated 18x18-bit multipliers. I used generate statements to create multiple instances of modules. At the top level, I generate 6 6-bit majority voters (voter6bitmaj):

 

    genvar i;
    generate
        for (i = 0; i < 36; i = i + 6) begin
                voter6bitmaj voter6(prod1[i+5:i], prod2[i+5:i], prod3[i+5:i],
                                                voted[i+5:1], errsyn[i/6], voterr[i/6]);
        end
    endgenerate



That "voted" argument indexing looks wrong.  Shouldn't it be:

voted[i+5:i] // i.e. 'i' instead of '1' as the LSB?

 

Regards,

 

Mark

 

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Moderator
Moderator
6,413 Views
Registered: ‎07-21-2014

@space_boy

 

I can see that the 5th net of voted port is connected to ground, can you check the load of this signal? I guess the load is trimmed from the design and then tool removed the associated load.

Capture.PNG

 

Thanks,
Anusheel
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Participant
Participant
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Registered: ‎11-21-2007

I don't really understand the question. Why would synthesis trim an arbitrary signal from the design? The 5th net isn't there due to the missing output signal from an embedded module.

 

Also, as I mentioned, I have tweaked the design slightly in various ways, but if I'm still using nested generate statements, there is always a signal left unconnected somewhere else. For example, in one case one of the inputs to one of the high level voter6bitmaj modules isn't connected. If I remove one of the generate statements and instantiate the modules at that level using numeric constants, the design is synthesized complete. Presumably the load on signals would be the same.

 

I know it's usually a poor excuse to blame the "compiler," but it makes me suspect there is a problem with synthesis of nested generate statements or nested modules containing generate statements.

 

Ron

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Highlighted
Scholar
Scholar
11,767 Views
Registered: ‎09-16-2009

@space_boy wrote:

I have a Verilog design which is a TMR experiment which sends triplicated signals to a hierarchy of voter modules. The signals represent 36-bit products of triplicated 18x18-bit multipliers. I used generate statements to create multiple instances of modules. At the top level, I generate 6 6-bit majority voters (voter6bitmaj):

 

    genvar i;
    generate
        for (i = 0; i < 36; i = i + 6) begin
                voter6bitmaj voter6(prod1[i+5:i], prod2[i+5:i], prod3[i+5:i],
                                                voted[i+5:1], errsyn[i/6], voterr[i/6]);
        end
    endgenerate



That "voted" argument indexing looks wrong.  Shouldn't it be:

voted[i+5:i] // i.e. 'i' instead of '1' as the LSB?

 

Regards,

 

Mark

 

View solution in original post

Highlighted
Participant
Participant
6,397 Views
Registered: ‎11-21-2007
Sharp eye!! How long would I have looked at this code w/o seeing that? At first I couldn't see how that would effect such a design anomaly, but this certainly would overload some bits in voted...

Once again, it's a poor player who blames his instrument (compiler). :-(

Thanks for the help!
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Moderator
Moderator
6,326 Views
Registered: ‎07-21-2014

@space_boy Can you please close this thread by marking Mark's answer as accepted solution which helped you to resolve the issue?

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