Vivado creates netlist with inputs shorted together

[cliffordwolf]

Vivado 2013.4 creates a netlist containing the following nonsense (see the assignments to <const0>) from the attached design.

// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec  9 17:26:26 MST 2013
// Date        : Sun Dec 29 22:26:35 2013
// Host        : euklid running 64-bit Ubuntu 12.04.3 LTS
// Command     : write_verilog -force netlist.v
// Design      : issue_010
// Purpose     : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
//               IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
//               design files.
// Device      : xc7k70tfbg676-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* use_dsp48 = "no" *)
(* STRUCTURAL_NETLIST = "yes" *)
module issue_010
   (a,
    b,
    y);
  input [5:0]a;
  input [3:0]b;
  output [89:0]y;

  wire \<const0> ;
  wire [0:0]\^a ;
  wire xlnx_opt_;
  wire xlnx_opt__1;
  wire [89:0]y;

  assign \<const0>  = a[3];
  assign \<const0>  = a[2];
  assign \<const0>  = a[1];
  assign \<const0>  = b[3];
  assign \<const0>  = b[2];
  assign \<const0>  = b[1];
  assign \<const0>  = b[0];
  assign \^a [0] = a[0];
IBUF IBUF
       (.I(\<const0> ),
        .O(xlnx_opt_));
...

 This netlist was generated using the following shell command:

/opt/Xilinx/Vivado/2013.4/bin/vivado -mode batch -source script.tcl

I have a couple more Vivado and XST bugs to report. Is this the right place to post them? I also have some ISIM bug reports. Should I post them in the "Simulation and Verification" forum? Or is there a special communications channel for bug reports?

EDIT: Unfortunately I can not attach the files. I always get "The contents of the attachment doesn't match its file type." messages. So here is the content of script.tcl:

read_verilog issue_010.v
synth_design -part xc7k70t -top issue_010
write_verilog -force netlist.v

 And here is the content of issue_010.v:

(* use_dsp48="no" *)
module issue_010(a, b, y);
  input [5:0] a;
  input [3:0] b;

  // I have no clue why but Vivado 2013.4 generates a netlist containing:
  //
  //   assign \<const0>  = a[3];
  //   assign \<const0>  = a[2];
  //   assign \<const0>  = a[1];
  //   assign \<const0>  = b[3];
  //   assign \<const0>  = b[2];
  //   assign \<const0>  = b[1];
  //   assign \<const0>  = b[0];
  //
  //   IBUF IBUF
  //         (.I(\<const0> ),
  //          .O(xlnx_opt_));

  wire [80:0] y0;
  wire [4:0] y1;
  wire [3:0] y2;

  output [89:0] y;
  assign y = {y0,y1,y2};

  assign y0  = 0;
  assign y1  = {4{{3{b}}}};
  assign y2  = 4'b1000 * a;
endmodule

[vemulad]

Hi,

assign y2  = 4'b1000 * a;

Result of 6-bit expression is truncated to fit in 4-bit target.

assign y1  = {4{{3{b}}}};

Result of 48-bit expression is truncated to fit in 5-bit target.

Check these in the code.

Thanks,

Deepika.

[cliffordwolf]

Hmm..

Result of 6-bit expression is truncated to fit in 4-bit target.

Result of 48-bit expression is truncated to fit in 5-bit target.  

I do not get this messages. Are you using a different script or command line? (In know that XST generates such messages, but this is a report about Vivado.) However, this version of the test case should not have the issue and still produces the same flawed output:

(* use_dsp48="no" *)
module issue_010(a, b, y);
  input [5:0] a;
  input [3:0] b;

  wire [80:0] y0;
  wire [4:0] y1;
  wire [3:0] y2;

  wire [47:0] tmp1;
  wire [5:0] tmp2;

  output [89:0] y;
  assign y = {y0,y1,y2};

  assign y0  = 0;
  assign tmp1  = {4{{3{b}}}};
  assign tmp2  = 4'b1000 * a;

  assign y1 = tmp1[4:0];
  assign y2 = tmp2[3:0];
endmodule

However, I have to add that also the original version is correct Verilog. Par. 5.6 from The Verilog Standard IEEE Std 1364-2005 clearly states: 

If the width of the right-hand expression is larger than the width of the left-hand side in an assignment, the
MSBs of the right-hand expression will always be discarded to match the size of the left-hand side.
Implementations are not required to warn or report any errors related to assignment size mismatch or
truncation. Truncating the sign bit of a signed expression may change the sign of the result.

So I have to strongly object to the notion that above messages are valid reason to generate invalid output.

Also note that I'm not looking for a work around or support in any way. (This test case is very unstable and even small changes will make the behavior go away anyways.) I'm trying to report a bug so Xilinx can improve their product by fixing it in the next version of the software.

[driesd]

Hi Clifford,

first of all, my sincere apologies that so far nobody took the responsibility to investigate and file a CR.

Please do keep your bug reports coming!

We highly appreciate such clear-cut cases with small testcases. That makes filing a CR much easier for us & for development to better understand the issue and resolve it.

I ran an equivalence check against a generated verilog netlist of 2014.1, 2014.2 RC and 2014.3 alpha.

I also checked with use_dsp48 = yes and no.

In all cases the behaviour was the same and the netlist does not match the RTL code. (there was a small difference between yes and no)

I filed CR799205 to get this fixed in our tools. Unfortunately I can't promise that it will make 2014.2 as we are getting relative close to release data. I do hope they can solve it by 2014.3.

Best regards

Dries

[driesd · Accepted solution]

FYI

I just confirmed that this bug has been fixed in an internal build of Vivado 2014.3.

This version is scheduled to be released in October.

Best regards

Dries