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Adventurer
Adventurer
118 Views
Registered: ‎07-25-2018

Vivado error for typdef in system verilog

I have a .svp file in which I have the below typedef enum and vivado is thorwing a compilation error.

typedef enum logic [1:0]
{ENET = 2'h0,
IPV4 = 2'h1,
IPV6 = 2'h2,
MPLS = 2'h3} pkt_hdr_e;

[HDL 9-806] Syntax error near "logic". ["/home/vinit.apte/zipline/Project-Zipline/rtl/cr_cceip_64_support/cr_cceip_64_support_regsPKG.svp":15]

I have changed the file property to System verilog. NOt sure why is this hard for vivado to compile.

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6 Replies
Scholar markcurry
Scholar
91 Views
Registered: ‎09-16-2009

Re: Vivado error for typdef in system verilog

For your enum_base_type, try using a bit, instead of logic.  I know this works in Vivado.

The SystemVerilog standard is a little unclear here, IMHO:  Legal enum_base_types are listed as integer_atom_type (does NOT include logic), or integer_vector_type (does include logic).  But in my mind the enumeration type checking, and type/value matching would get weird in the presence of 4-state values.  None of the examples in the standard use a 4-state type for the enum_base_type.

Regards,

Mark

 

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Participant steven_bellock
Participant
79 Views
Registered: ‎10-25-2018

Re: Vivado error for typdef in system verilog

@markcurry 

Check out section 6.19 of the 2017 LRM.

An enum declaration of a 4-state type, such as integer, that includes one or more names with x or z assignments shall be permitted.

// Correct: IDLE=0, XX='x, S1=1, S2=2 enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;
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Adventurer
Adventurer
48 Views
Registered: ‎07-25-2018

Re: Vivado error for typdef in system verilog

I tried bit instead of logic but it still fails to compile. Any flags I should use to make this work

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Adventurer
Adventurer
46 Views
Registered: ‎07-25-2018

Re: Vivado error for typdef in system verilog

Here is the file attached. You can try compiling it at your end and let me know.

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Scholar markcurry
Scholar
44 Views
Registered: ‎09-16-2009

Re: Vivado error for typdef in system verilog

Try just renaming the file to .sv?  I only use non-project batch mode - in this mode if you filename is *.sv, SystemVerilog compilation is automatically turned on.

You mentioned you "changed the file property to System verilog" - implying Vivado project mode.  But I'm wondering if somehow SystemVerilog mode isn't being fully/correctly turned on.

Here's one of my examples that we've been using within Vivado (Synthesis) for many years, without isses.

  typedef enum bit [ 2 : 0 ]
  {
     CC_SUCCESS = 'b000,
     CC_UNSUPPORTED = 'b001,
     CC_ABORT  = 'b100
  } cc_comp_status_t;

Regards,

Mark

 

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Scholar markcurry
Scholar
36 Views
Registered: ‎09-16-2009

Re: Vivado error for typdef in system verilog

Looking at your example - there's no scope defined.  Are you planning on compiling all those typedefs into global name space?  I suggest otherwise - Put all those enum definitions in a package.  Enum literals are troublesome with respect to name space.  Best to keep them segregated. (i.e. you don't want an enum Literal "CMD", or "KEY" living in global name space).

I've no idea if this is related to your troubles or not, but thought I'd offer the suggestion.

Regards,

Mark

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