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Visitor
Visitor
4,499 Views
Registered: ‎02-21-2012

Vivado incorrect time calculation

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Hi,

 

When I use a counter to count certain time interval in my code, I like to derive the range of that counter based on two constants, the period of time I want to count and the period of my clock (they are sometimes generics into the module instead of constants), example: 

constant c_period_to_count : time := 1 ms;

constant c_clock_period : time := 10 ns;

signal count_to_1ms : natural range 0 to (c_period_to_count /  c_clock_period) - 1;

 

I have been doing this on XST for years and seem to work fine.  I recently started using vivado and seem to be running into a problem with this.

 

Here is an example:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

 

....

 

 

signal test1 : natural range 0 to (1 ms / 1 us) := 0;
signal test2 : natural range 0 to (100 us / 10 ns) := 0;

begin

process (i_clk)

begin

if rising_edge(i_clk) then

test1 <= test1 + 1;

test2 <= test2 + 1;

end if;

end process;

 

In my synthesis report I find a warning on line (test2<= test2+1) that the assigned value '1' is out of range [Synth 8-3512].  It seems like Vivado didn't calculate 100 us / 10 ns correctly, however it didn't have a problem with signal test1 (1 ms / 1 us).  There are no other warnings that something seriously went wrong with the range synthesis on test1.

 

btw I am using version 2016.2 of vivado.

 

Thanks

Donald

 

1 Solution

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Moderator
Moderator
8,088 Views
Registered: ‎07-21-2014

Re: Vivado incorrect time calculation

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@donaldz425

 

As detailed in Section "VHDL Constructs Support Status" in the Vivado Synthesis user guide UG901, TIME data type is not supported and should not be used for logic inference.

Vivado Synthesis tool will try to elaborate the design based on RTL, but the Synthesis engine may not create the expected logic.

 

Thanks,
Anusheel
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Moderator
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Registered: ‎01-16-2013

Re: Vivado incorrect time calculation

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Moderator
Moderator
8,089 Views
Registered: ‎07-21-2014

Re: Vivado incorrect time calculation

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@donaldz425

 

As detailed in Section "VHDL Constructs Support Status" in the Vivado Synthesis user guide UG901, TIME data type is not supported and should not be used for logic inference.

Vivado Synthesis tool will try to elaborate the design based on RTL, but the Synthesis engine may not create the expected logic.

 

Thanks,
Anusheel
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Scholar
Scholar
4,393 Views
Registered: ‎04-26-2012

Re: Vivado incorrect time calculation

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@donaldz425  "I like to derive the range of that counter based on two constants, the period of time I want to count and the period of my clock (they are sometimes generics into the module"

 

I typically do this sort of calculation with reals instead of time, which seems to still work in Vivado.

 

I posted a short example (computing counter lengths) on this 2015 thread regarding problems with physical types and time in Vivado synthesis:

https://forums.xilinx.com/t5/Synthesis/Vivado-Synth-Bug-in-handling-physical-types/m-p/557049

 

"I have been doing this on XST for years and seem to work fine.  I recently started using vivado and seem to be running into a problem with this."

 

My experience with Vivado has been that VHDL code which has worked for a dozen years in XST, and decades in Synplify, is horribly broken by Vivado Synthesis, often failing silently (no synthesis errors) and producing bad hardware.

 

Xilinx doesn't seem to care, as they have focused their development resources on HLS, SDAccel and the like; the result is a crippled synthesizer, with useless documentation, that they refuse to fix.

 

-Brian

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Visitor
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Registered: ‎02-21-2012

Re: Vivado incorrect time calculation

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Thanks everyone for the responses.  Looks like the answer is don't use time type anymore if you want to use vivado synthesizer.... 

 

I can accept Xilinx's decision to no longer support time type in vivado, but like said, it could have been handled better.  The tool should throw an error when a time data type is used or it encounters a time calculation it cannot perform.  Right now the tool seem to just silently make up some bad logic, and sends the designer down the dark path of trying to figure out why his simulation and synthesis don't match.  Is there anyone from Xilinx we can escalate this to?  It seem like it would be a pretty simply fix...  I have been pretty happy with XST with ISE, should I go back to using synplify now that we are using vivado?

 

Thanks

 

Donald

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