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Explorer
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Registered: ‎05-07-2012

Vivado place and route error

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Hello,

 

I'm trying to build my first design in Vivado, the tool that is supposed to save me so much time but so far has wasted about a month while Xilinx support staff works on resolving the many bugs that still exist in the tool. 

 

So, my place and route is bombing with the following error,

 

[Place 30-99] Placer failed with error: 'Exit after global placer'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

 

I have no other errors, no critical warnings and about 38 place and route warnings.  Near as I can tell Vivado is telling me that it has no idea why it stopped and I'm on my own to figure it out.  Using this tool is starting to remind me of the old Foundation days when Xilinx tools sucked sooooo bad. 

 

Does anyone have any ideas on how I can get more information out of Vivado as to why it can't complete the build?

 

Thank you.

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Explorer
Explorer
24,588 Views
Registered: ‎05-07-2012

Re: Vivado place and route error

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The webcase engineer ran the design through a yet to be released Vivado version 2015.1 and the reported info is below.

 

Apparently there are two too many clocks in region X0Y0.  At least now I have something to resolve.

 
 
ERROR: [Place 30-177] Unroutable Placement! There are more clocks in the clock region than the maximum number of allowed clocks per clock region.
 
                Displaying only the first 20 drivers as list of drivers is too long
                emc/ecg/U0/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
                emc/ecg/U0/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
                emc/tmem/U0/rgmii_interface/txdata_out_bus[3].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y58
                emc/tmem/U0/rgmii_interface/txdata_out_bus[2].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y57
                emc/tmem/U0/rgmii_interface/txdata_out_bus[1].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y56
                emc/tmem/U0/rgmii_interface/txdata_out_bus[0].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y55
                emc/tmem/U0/rgmii_interface/rgmii_txc_ddr (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y60
                emc/tmem/U0/rgmii_interface/rgmii_tx_ctl_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y59
                fcg/U0/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLKB) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLK) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLKB) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLK) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].idelay_s (IDELAYE2.C) is locked to IDELAY_X0Y39
                misor/sr1/dsrx/loop0[1].idelay_m (IDELAYE2.C) is locked to IDELAY_X0Y40
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y37
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLKB) is locked to ILOGIC_X0Y37
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLK) is locked to ILOGIC_X0Y37
 
From the error message it looks like the number of clocks entering a clock region are more than the allowed number.
I then ran report_clock_utilization command to see the clock utilization in each clock region. Below is a section of the report which shows that the clock region X0Y0 has 14 global clocks however there are only 12 resources available. Out of these 14 three are instantiated BUFHCE’s in the design.
 
7. Clock Regions : Key Resource Utilization
-------------------------------------------
 
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E1   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |   14 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |   16 |    50 |    7 |    50 |    0 | 21600 |    0 |  3200 |    0 |    60 |    0 |    30 |    0 |    60 |
| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    0 |    20 |    0 |    40 |
| X0Y1              |    5 |    12 |    1 |     4 |    0 |     2 |    1 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    5 |    50 |    6 |    50 |    0 | 33600 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y2              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 28800 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y3              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 28800 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y4              |   10 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     1 |    5 |    50 |    5 |    50 |    0 | 20400 |    0 |  3000 |    0 |    50 |    0 |    25 |    0 |    60 |
| X1Y4              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    0 |    20 |    0 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: Vivado place and route error

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s,

 

Have you looked at the log file?  Please post it here.  Which version are you using?  Which device?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎05-07-2012

Re: Vivado place and route error

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Thanks for the help.  I've attached the implementation runtime log. 

 

I'm using Vivado 2014.4 and an Artix 7 (200T) on the AC701 board.

 

 

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: Vivado place and route error

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OK,

 

Looks like the constraints are preventing placement of some asynchronous (clock crossing domain) synchronizers (WARNINGS).  So next step is to post the constraints file.

 

If it were me trying to debug, I would remove any location constraints until I found the ones that were causing the warnings.  I would then go and find out what the intent of those constraints were, and figure out how to do what I want.

 

There is also a non-clock capable io pin being used for an input clock, and thay cause a problem later, as timing may not be guaranteed.

 

So the reason why it crashes, is it tells you it can't place the synchronizers (WARNINGS).  After it has told you that it will fail, it goes ahead anyway to the next step.  Why?  Well, often logic is optimized out in later steps, so it might as well just forge ahead.  Or maybe you know better (it is a warning after all, not an error at that point).  An warning in an early stage may become an error at a later stage (or a crash, as in this case).  The bug is the error was not recognized (reported) in time.  But the cause is evident (cannot implement synchronizer as it conflicts with the constraints).

 

In that sense, Vivado is more advanced than the older tools (it attempts to do more work).  It is also aware of clock domain crossings, and it will pester you with warnings until you have a legitimate synchronous design (the old tools didn't care, and would gladly send you into a hell of poor asynchronous design realizations).

 

So think of Vivado as enforcing good synchronous digital design techniques, and preventing you from wasting time later fixing problems.  Those WARNINGS are your friends - they direct you to look at ways to NOT do poor design (unless you really know better, as you can forge ahead with thousands of warnings, and the tool will still try to do the best it can).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎05-07-2012

Re: Vivado place and route error

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Thanks for your help Austin. 

 

I've done a lot of FPGA work over the years.  I avoid placement constraints like the plague.  Everything is synchronous.  I pipeline to solve timing problems.  I can't remember the last time that I had a post fit problem.  With this Vivado tool constraints are scattered all over the place.  There is my constraints file and then there are constraint files buried in core folders.  Then there are constraints buried in XML files.  The AC701 board file also has constraints in it and that file is buried deep in the Vivado hierarchy.  ALL of these warnings that you mention are Xilinx core constraint related and are buried deep in the bowels of the files that the tool is generating.  They are not mine.  I don't even understand what the hell they are talking about half the time.  For example, what's a synchronizer? To my knowledge, I've never instantiated a synchronizer in my life.  I instantiate FIFOs, RAMS, Flip Flops, clocks, SERDES, Buffers, ... This tool is way too complex and so far it hasn't saved me from anything except getting this project done in a timely manner.  I have another HDL design as part of this project which was done in ISE.  It was completed in short order. 

 

Well, I'll go digging around all these xdc files and see if I can find anything related to these warnings.

 

Thanks again.

 

 

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: Vivado place and route error

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s,

 

If they are in the IP blocks, then it is off to support to get it resolved then.

 

Let me know if that is not working.

 

As I have posted before, if you place urgency on the problem, the support system escalates the response (involves more experts, place a priority on it).

 

So, even here on the forum, a problem that requests escalation is treated with more than a casual reply.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎05-07-2012

Re: Vivado place and route error

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Austin,

 

I'm looking and other than pins, I don't have any location constraints and I don't see any location constraints in the core xdc files.  But I'll keep looking.

 

 

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Registered: ‎05-07-2012

Re: Vivado place and route error

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Thanks, Austin, I did open a webcase and am waiting to hear from them.

 

s

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: Vivado place and route error

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OK,

 

Let us know how it goes.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎05-07-2012

Re: Vivado place and route error

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The webcase engineer ran the design through a yet to be released Vivado version 2015.1 and the reported info is below.

 

Apparently there are two too many clocks in region X0Y0.  At least now I have something to resolve.

 
 
ERROR: [Place 30-177] Unroutable Placement! There are more clocks in the clock region than the maximum number of allowed clocks per clock region.
 
                Displaying only the first 20 drivers as list of drivers is too long
                emc/ecg/U0/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
                emc/ecg/U0/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
                emc/tmem/U0/rgmii_interface/txdata_out_bus[3].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y58
                emc/tmem/U0/rgmii_interface/txdata_out_bus[2].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y57
                emc/tmem/U0/rgmii_interface/txdata_out_bus[1].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y56
                emc/tmem/U0/rgmii_interface/txdata_out_bus[0].rgmii_txd_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y55
                emc/tmem/U0/rgmii_interface/rgmii_txc_ddr (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y60
                emc/tmem/U0/rgmii_interface/rgmii_tx_ctl_out (ODDR.C) is provisionally placed by clockplacer on OLOGIC_X0Y59
                fcg/U0/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLKB) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_s (ISERDESE2.CLK) is locked to ILOGIC_X0Y39
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLKB) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].iserdes_m (ISERDESE2.CLK) is locked to ILOGIC_X0Y40
                misor/sr1/dsrx/loop0[1].idelay_s (IDELAYE2.C) is locked to IDELAY_X0Y39
                misor/sr1/dsrx/loop0[1].idelay_m (IDELAYE2.C) is locked to IDELAY_X0Y40
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y37
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLKB) is locked to ILOGIC_X0Y37
                misor/sr1/dsrx/loop0[0].iserdes_s (ISERDESE2.CLK) is locked to ILOGIC_X0Y37
 
From the error message it looks like the number of clocks entering a clock region are more than the allowed number.
I then ran report_clock_utilization command to see the clock utilization in each clock region. Below is a section of the report which shows that the clock region X0Y0 has 14 global clocks however there are only 12 resources available. Out of these 14 three are instantiated BUFHCE’s in the design.
 
7. Clock Regions : Key Resource Utilization
-------------------------------------------
 
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E1   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |   14 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |   16 |    50 |    7 |    50 |    0 | 21600 |    0 |  3200 |    0 |    60 |    0 |    30 |    0 |    60 |
| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    0 |    20 |    0 |    40 |
| X0Y1              |    5 |    12 |    1 |     4 |    0 |     2 |    1 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    5 |    50 |    6 |    50 |    0 | 33600 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y2              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 28800 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y3              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 28800 |    0 |  5600 |    0 |   100 |    0 |    50 |    0 |   100 |
| X1Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |    0 |    40 |    0 |    80 |
| X0Y4              |   10 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     5 |    0 |     1 |    5 |    50 |    5 |    50 |    0 | 20400 |    0 |  3000 |    0 |    50 |    0 |    25 |    0 |    60 |
| X1Y4              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    0 |    20 |    0 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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