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Vivado stalling 2018.2 - error messaging broken

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Adventurer
Posts: 54
Registered: ‎01-09-2018
Accepted Solution

Vivado stalling 2018.2 - error messaging broken

[ Edited ]

Issue and cause:

I have now come to the point where I see 20 scrscanner.exe taking each 2-5% if my CPU or >3Mb RAM

so it is not a mystery why it stalls the machines

 

My equipments:

I have a quad processor windows 10 Papillon HP laptop that is fairly new

 

Question for the Vivado designers:

I am not sure why they are trying to have the parallelism on a sequential operating system that only forces to have the OS spending more time in making interrupts all the time?

Additionally for such applications such as Vivado would it not be faster to implement it in assembler?

 

Workaround:

One way I am now trying is to replace my design files with empty dummies and then build the block diagram and then populate the files one by one forcing the Vivado to only work on one file at the time

 

Log:

Sep 12 2018, 12:01 PM              Open the project with design files stripped from content (only pins in and out)

Sep 12 2018, 12:05 PM              Block design is open it did not take 2 hours or more!

Sep 12 2018, 12:17 PM              Finished to wire the new block and started successful synthesis run

                                                   so far the system is stable - the workaround allows to correct errors without wasting hours..

                                                   so far the project is finally build - the block design is wired at last but took fairly long

Workaround:

The srcscanner parallelism issue seem to be gone using the patch I found here PATCHER :
https://www.xilinx.com/support/answers/71064.html
download then run as admin

 

Log:

 Sep 12 2018, unspecified         vivado is far faster to handle I finally can start the synthesis, yet that stalls after 4 hours

                                                  it was the same design that succesfully passed the implementation and build but it had to be 

                                                  flattened version (because of scalability requirements I have)

 

My code is flattened (no hierarchy):

just defines a 80x640 array of connected units :


Instances Instance0_0( C[1:0], z0_0[1:0], s0_0[1:0], y0_0[1:0], x0_0[1:0], x0_1[1:0], y1_0[1:0], z1_0[1:0], s0_1[1:0]);

to 

Instances Instance79_639( CC[1:0], z79_639[1:0], s79_639[1:0], y79_639[1:0], x79_639[1:0], x79_640[1:0], y80_639[1:0],z80_639[1:0], s79_640[1:0]);

 

and the connections between the units:


wire [1:0] x0_0, y0_0, z0_0;

to 

wire [1:0] x80_640, y80_640, z80_640;

 

Its simpler to handle flattened code for me because I use javascript to generate it (feel free to see my other post where I show how)

 

Log:

Sep 13 2018, around 3:00 PM     Build a clean project from scratch and reduced the size

Sep 13 2018, 11:47AM                 Synthesis is still not finished on that simple 50k blocs array after 9 hours

 

Target

XC7A200TSBG484 the Artix7 offers 134600 slices with 1 LUT + 2 FF

 

 Question

I passed the synthesis with a hierachy of 10x80x320x8x8 (<2hours!) instead of the current flattened version 640x80

Is there a reason why Vivado does not handle flattened hierarchies? 

Is the something in the settings I missed out?

 

Log:

Sep 13,2018 12:34 PM    Vivado is running for more than 10 hours and I need advice sorry for bothering everyone again~

 

Settings

trying to resynthesis using :

                                        Settings > Synthesis
                                               -flattenhierarchy = full (was rebuild)
                                               -fanout_limit = 1000000 (was 10'000)
                                               -directive= RuntimeOptimized

 

Log:

Sep 13,2018 3:21 PM    synthesis stalls its still running after 3 hours I stopped it - will rebuild in hierarchies seem no other way

 

Sep 13,2018 10:19 PM  smallest hierarchy 80x80 stalls but on rebooting the computer some error messages appeared helping to get the design more consistent - why they did not appear on the onset? The messages still apply to to the previous run a BRAM is mentioned when its in this run excluded by making the sub block with the problems the top hierarchy:  something is wrong with error reporting no wonder the designs stall when it should recognize the errors and stop instead of just idling and not give any message. This explains why designs then have synthesis working because they had 0 errors and is stalling on other designs that have hidden errors because i get no message and no way to guess, this shows that Vivado is not finding errors because the messaging seems broken!

 

Vivado 2018.2

messages: not one error

 

 trying the same project in ISE 4.2

 

Log:

 Sep 14,2018 8:22 AM        placed the 80x80 in the top module of an example project after installing ISE4.2 error messages work:

 

ISE 4.2 messages:

Compiling included source file 'top.v' ERROR:Xst:1152 - top.v Line 7. `timescale directive must be outside a module ERROR:Xst - top.v Line 37. parse error ERROR:Xst - top.v Line 38. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 38. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 39. parse error ERROR:Xst - top.v Line 39. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 39. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 40. parse error ERROR:Xst - top.v Line 40. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 40. parse error, expecting `error' or `','' or `')'' ERROR:Xst - top.v Line 57. parse error, expecting `','' or `';'' ERROR:Xst - top.v Line 58. parse error, expecting `','' or `';'' ERROR:Xst:938 - top.v Line 60. 'D' is not a vector etc.. about > 5000 errors and then it exited due to the max reached: ERROR:Xst:938 - top.v Line 6797. 'CC' is not a vector Module <top> compiled. FATAL_ERROR:Xst:parse.y:697:1.11 - Maximum number of errors (100) exceeded. Process will terminate. To resolve this error , please consult the Answers Database and other online resources at http://support.xilinx.com EXEWRAP detected a return code of '34' from program 'C:/xONE/ISE42/bin/nt/xst.exe' Done: failed with exit code: 0034.

 

 

Log:

Sep 15, 2018 1:14 PST AM      Vivado is not showing errors and stalls on too large designs but ISE 4.2 seems not to have any issues (see below)

 

example of error ISE reports that vivado failed to:

 ISE 4.2 was rebuilt in a few hours (Vivado too a few days) and opening the interfacte is in a few seconds (Vivado 3 min +) then it found heaps of errors that Vivado simply did not and kept stalling example:

 

got me a warning in ISE 4.2 (vivado did not give any warning):

WARNING:Xst:977 - UART.v Line 73. Extra digits in binary number

 

   data_bin[3:0] <=  4'b00000;

 

Log:

Sep 15, 2018 10:14 PST AM   something additional I found in a message was that every unit was infering a latch ??

 

latch inference:

one interesting error the ISE4.2 brought was that they actually infere 6400 latches from the design 80x80 bitslices

is that causing a panic in the tool I know that latches are not wanted in general  - how can I avoid it?

 

 

Log:

Sep 15, 2018 10:24 PST AM       redesign filling with dummy flip flops will build on vivado/ISE42/Quartus so I get more messages

 

am going to force a flip flop in each slice to help the synthesis panic less but if that works then what? My design will be far slower because signals have to travel through the flip flop array, I have to try it

 

or can anyone tell me how to avoid latch inference?

 

Log:

Sep 15, 2018 03:00  PST PM     See VivadoFailMessageCount.png after 4 hours I closed the synthesis it has 0 errors showing and the warnings count is 5+5+133=237. How can software fail to add numbers that is evading my understanding. I am still running the version with inserted flip flops it is now 3 hours .

It stalls no matter what I do ?

 

Log:

Sep 15, 2018 09:01  PST PM    Good news - I figured out the signification of the warning and it was that the latches where inferred because my blocks had outputs connected back to inputs because of erroneously swapping left and right. The synthesis engine wont cope with recursion and fails. Quartus actually once told a message on that and I remembered that was a similar issue. In fact I checked on a 4x4 reduced version so I was able to go though the wires one by one and noticed that left and right pins where swapped. The synthesis worked perfect once the error was found.

 

Solution

Using ISE4.2 verbose messages (warnings + errors) and checking the design for recursion errors. The synthesis tool follow the wires stupidely and if they check a path that goes back to the beginning they done realize their is a loop and stall because they turn in circles. Quartus di give a message about recursion error once so perhaps Xilinx could look into that occurrence I can gladly provide my files if aske.

 

In fact Vivado works if one does not make this particular stupid error I did..

 

hope this post helps other designers that are stuck like I was and wonder why the tool is stalling:

 

- check for recursions or it will infer latches and then it gets seriously lost in the loops he does not see

 

Thanks everyone for letting me post and that helped

VivadoFailMessageCount.png

Accepted Solutions
Adventurer
Posts: 54
Registered: ‎01-09-2018

Re: Vivado stalling 2018.2 - error messaging broken

Solution

Using ISE4.2 verbose messages (warnings + errors) and checking the design for recursion errors.

The synthesis tool follow the wires stupidely and if they check a path that goes back to the beginning they done realize their is a loop and stall because they turn in circles.

 

Quartus di give a message about recursion error once so perhaps Xilinx could look into that occurrence I can gladly provide my files if aske. In fact Vivado works if one does not make this particular stupid error I did.. hope this post helps other designers that are stuck like I was and wonder why the tool is stalling:

 

- check for recursions or it will infer latches or it gets seriously lost in the loops he does not see

 

Hope that helped

View solution in original post


All Replies
Adventurer
Posts: 54
Registered: ‎01-09-2018

Re: Vivado stalling 2018.2 - error messaging broken

Solution

Using ISE4.2 verbose messages (warnings + errors) and checking the design for recursion errors.

The synthesis tool follow the wires stupidely and if they check a path that goes back to the beginning they done realize their is a loop and stall because they turn in circles.

 

Quartus di give a message about recursion error once so perhaps Xilinx could look into that occurrence I can gladly provide my files if aske. In fact Vivado works if one does not make this particular stupid error I did.. hope this post helps other designers that are stuck like I was and wonder why the tool is stalling:

 

- check for recursions or it will infer latches or it gets seriously lost in the loops he does not see

 

Hope that helped

Adventurer
Posts: 54
Registered: ‎01-09-2018

Re: Vivado stalling 2018.2 - error messaging broken

[ Edited ]

[posted here by mistake - removed and added to the post Status : Design Initianization ERROR - no error messages  as "solution"]

 

apologies