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ojay77
Observer
Observer
581 Views
Registered: ‎04-25-2018

Vivado synthesis NOT matching Vivado simulation

I am working on a project where I receive ethernet video traffic, convert it to 128-bit chunks of data which I then write to memory. I have simulated my design and it behaved as I expected it but upon synthesizing and analyzing my signals on chipscope I am finding out a very strange Synthesis disparity with simulation. Specifically the issue is with a 'rden' signal that I'm generating (combinationaly) to request to read data from memory. The line is

"

assign data_mem_rd_en = !fifo_empty && !stop_fifo_read && !data_mem_valid && (memvld[15:1] == 15'b0);

"

Which simulates as expected but upon synthesis I'm finding that this signal is not being driven to logic high for very long periods of time when all the conditions for it are right. I was flabberghasted and even tried re-writing it in a combinational 'always' block as follows:

"

always@ (fifo_empty or stop_fifo_read or data_mem_valid or memvld)
begin
if ((fifo_empty == 1'b0) && (stop_fifo_read == 1'b0) && (data_mem_valid == 1'b0) && ((memvld == 16'd0) || memvld == 16'd1)) begin
data_mem_rd_en = 1'b1; end
else begin data_mem_rd_en = 1'b0;
end
end

"

After change the 'data_mem_rd_en ' type to reg (from wire) but it still behaves the same in hardware.

The design is targeting a Kintex 7 device.

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klumsde
Moderator
Moderator
542 Views
Registered: ‎04-18-2011

what do you see in the simulation of the synthesized netlist? I don't know enough about the rest of the design to say why this isn't working. likely this is not the problem. you need to look at what is driving this signal. It will require some detective work to work out what can be going on. One suggestion is to make this functionality synchronous to the clock. draw a proper timing diagram for this as well so we can trace what is meant to happen then we come up with reasons why it is misbehaving.
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