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Visitor chrbirks
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Registered: ‎07-27-2017

Vivado synthesis engine

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Hi

I have been searching for information about which algorithms and methods Vivado uses for synthesis (and routing) but I have found nothing else than a forum post mentioning that it's based on Berkeley's ABC system. I imagine that the routing algorithm is closed source as it might reveal too much about the bitstream format but is there any information available about how it does synthesis?

 

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Advisor evgenis1
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Registered: ‎12-03-2007

Re: Vivado synthesis engine

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Hi @chrbirks ,

There are bits and pieces of publicly available information (forums and datasheets) that mention Verific Verilog synthesis engine [link] being used by Vivado.

As far as Vivado place&route engine, there isn't much information either. There is a short product brief [link] that discusses Analytical P&R technology, which superseeds gradient and successive over-relaxation approach in earlier ISE.

 

Thanks,

Evgeni

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Advisor evgenis1
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Registered: ‎12-03-2007

Re: Vivado synthesis engine

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Hi @chrbirks ,

There are bits and pieces of publicly available information (forums and datasheets) that mention Verific Verilog synthesis engine [link] being used by Vivado.

As far as Vivado place&route engine, there isn't much information either. There is a short product brief [link] that discusses Analytical P&R technology, which superseeds gradient and successive over-relaxation approach in earlier ISE.

 

Thanks,

Evgeni

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Visitor chrbirks
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Registered: ‎07-27-2017

Re: Vivado synthesis engine

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Hi @evgenis1 

Thank you for the info.

For anyone interested, I was able to dig a little more into their Analytical Place and Route algorithm but was only able to find this old white paper WP416 which describes roughly the same as evgenis1's link. But I did find a PDF from Western University in Ontario describing FPGA placement/routing in general and both simulated annealing and analytic placement.

 

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