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aholme
Visitor
Visitor
2,159 Views
Registered: ‎06-29-2018

Vivado synthesis incorrect since 2018.3 and still in 2019.2

Create a new Vivado project, add the 3 attached files (top.v, success.v and failure.v), run synthesis and look at the schematic.  Modules "success" and "failure" are logically equivalent; however, since 2018.3, Vivado has incorrectly synthesised module "failure".

The problem did not occur in 2018.2, was introduced with 2018.3 and is still present in 2019.2

Target FPGA is xcvu440-flga2892-1-c but that seems not critical.

 

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8 Replies
skeptonomicon
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Visitor
2,123 Views
Registered: ‎12-09-2019

Please include a test bench that shows the failure. Without a test bench, we can't know what stimulaus to provide to generate the difference.

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aholme
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Visitor
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Registered: ‎06-29-2018

You don't need a testbench to see the problem.  The schematic shows the failing module is not sensitive to all the inputs as it should be.  See attached png.  And BTW - in case you haven't looked - the code is trivial.

schematic_2019p2.png
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pulim
Xilinx Employee
Xilinx Employee
2,110 Views
Registered: ‎02-16-2014

Hi @aholme 

 

Thanks for reporting this issue. I am able to reproduce this issue at my end in 2019.2

Debugging this issue and will keep you posted with updates.

 

Thanks,

Manusha

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aschule
Xilinx Employee
Xilinx Employee
2,100 Views
Registered: ‎04-19-2010

Hello, I have been able to reproduce the problem and verify that the logic is incorrect using formal verification.  The problem does appear to be that the "finished" and "list_valid" inputs are not driving the "failure" module any longer.  I have filed a CR for this and assigned to development.

 

I see if I can find any workarounds for this next.

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aholme
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Registered: ‎06-29-2018

Thank you Manusha and aschule.  Module "success" is the workaround we are using.  Please find attached an updated version of the demo, including a testbench.  I have also fixed the SystemVerilog-style implicit port connections in top.  If you run a behavioral simulation, it passes.  If you run a post-synthesis functional simulation, it fails.

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aschule
Xilinx Employee
Xilinx Employee
2,071 Views
Registered: ‎04-19-2010

I tried a few different workarounds none of them worked.  The next thing I was going to try was to break up next[0] and next[1] into different always blocks, but I can see that is what the module success already does. I have let the developer know that this is the problem.

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markcurry
Scholar
Scholar
2,056 Views
Registered: ‎09-16-2009

Could this be related to the state machine problem here?:

https://forums.xilinx.com/t5/Synthesis/Vivado-2018-x-and-Verilog-case-statements-looks-like-an-errata/m-p/970365/highlight/true#M30979 

That thread discusses another RTL/netlist mismatch related to the Vivado State Machine optimizer.  An AR was published as well:

https://www.xilinx.com/support/answers/72586.html 

This was supposed to be fixed in Vivado 2019.1, but I've not yet verified this.  

We've globally turned off FSM optimizations in our Vivado designs because of this bug.  I'm wondering if this new bug @aholme has posted here is related.

Can someone try the testcase with FSM optimization turned off, and see if the mismatch still persists?

Regards,

Mark

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aschule
Xilinx Employee
Xilinx Employee
2,040 Views
Registered: ‎04-19-2010

Turning off the state machine was one of the expirements that I tried and it did not fix the issue.  The problem seems to be how the next signal is being assigned.

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