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Observer
Observer
3,454 Views
Registered: ‎11-07-2016

Vivado synthesis result logic topology not what is in RTL

Looking at the results of Vivado synthesis I get the following:

 

A signal, let's call it SX, is in the RTL an output of module MA.  

 

When I make a schematic of my worst timing path from synthesis, the schematic has SX coming out of module MB.  In the RTL SX is neither an input to or an output from MB.

 

Is Vivado being "really smart" and has determined that the best logic is one in which SX is an output of MB and not MA?  Or, is this a sign that the synthesis is going very wrong? 

 

Your comments will be very valuable to me.

 

Thanks.

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Moderator
Moderator
3,439 Views
Registered: ‎11-09-2015

Hi @jsduran4xilinx,

 

It is not easy to say just from your description. If you send a test case we could explain you what is going on in detail.

 

But yes, Vivado can do optimization without changing the behavior of your design.

 

One way to check that the behavior is correct is to compare the behavioral and post-synthesis simulation.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Teacher
Teacher
3,413 Views
Registered: ‎03-31-2012

@jsduran4xilinx yes, when flatten & rebuild option is set in synthesis, sometimes cells move to different hierarchies because of the optimizations. This is normal albeit unexpected and confusing at times.

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