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Registered: ‎01-24-2019

Vivado (un)supported SV language construct "const constant"

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Hello everyone,

In the Vivado UserGuide UG901 - 2019.2 in table 8-1 is stated, that "const constants" are a not supported SystemVerilog construct in Vivado. In my code I defined some constants in a package like

const logic [7:0] SOME_SYMBOL = 8'b1010_1010;

and it seems to simulate, synthesize and implement.

  1. Does somebody know, whether the documentation is out of date?
  2. Does "const constant" refer to an other construct? If yes, can you please give an example.
  3. What is the best practise to define constants? Is it like in the example above or as a define? What is the impact on synthesized design size and speed. Are there any other aspects I am not aware of?

Thanks in advance. Stay healthy.

Tobias

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Registered: ‎07-23-2019

 

"SystemVerilog does not allow const variables in constant expressions, even if they are declared with a constant expression for a value"

Const and constant are different things in SystemVerilog. what you have there is a const variable. Therefore, you can use it freely, except in a constant expression, for example the below would be invalid:

wire [SOME_SYMBOL:0] array;

Because the array bounds must be a constant expression 

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Highlighted
409 Views
Registered: ‎07-23-2019

 

"SystemVerilog does not allow const variables in constant expressions, even if they are declared with a constant expression for a value"

Const and constant are different things in SystemVerilog. what you have there is a const variable. Therefore, you can use it freely, except in a constant expression, for example the below would be invalid:

wire [SOME_SYMBOL:0] array;

Because the array bounds must be a constant expression 

View solution in original post

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Registered: ‎01-24-2019
Thanks for the quick clearification.
Tobias
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