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1,117 Views
Registered: ‎10-01-2019

Vivado warning

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I am trying to synthesize following code in vivado 2017.4

module fir_q1#(parameter width=16
)(
input clk,
input signed [width-1:0]x,
output reg signed [31:0] out
);
reg [width-1:0] flipflop [4:0];
reg signed [15:0] coff [0:5];
integer i;
initial
begin
$readmemb ("memoryh.mem",coff);
for (i=0;i<6;i=i+1)
begin
$display("value in mem at i %0d",coff[i]);
end
end
always@(posedge clk )
begin
out=x*coff[0]+flipflop[0]*coff[1]+flipflop[1]*coff[2]+flipflop[2]*coff[3]+flipflop[3]*coff[4]+flipflop[4]*coff[5];
flipflop[0]<=x;
flipflop[1]<=flipflop[0];
flipflop[2]<=flipflop[1];
flipflop[3]<=flipflop[2];
flipflop[4]<=flipflop[3];
end
endmodule

But there are warnings like:

WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory name 
WARNING: [Synth 8-6014] Unused sequential element flipflop_reg[3] was removed. 
WARNING: [Synth 8-6014] Unused sequential element flipflop_reg[2] was removed. 
WARNING: [Synth 8-6014] Unused sequential element flipflop_reg[1] was removed. 
WARNING: [Synth 8-6014] Unused sequential element flipflop_reg[0] was removed. 
INFO: [Synth 8-256] done synthesizing module 'fir_q1' (1#1) 
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[15]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[14]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[13]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[12]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[11]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[10]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[9]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[8]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[7]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[6]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[5]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[4]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[3]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[2]
WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[1]

WARNING: [Synth 8-3331] design fir_q1 has unconnected port x[0]

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1 Solution

Accepted Solutions
nlotankar
Visitor
Visitor
990 Views
Registered: ‎11-14-2019

Hi,

The memory in your code infers to distributed RAM rather than block ram. This is causing issue while synthesizing.

Please take a look at below modified code to infer block RAM, I have added a few signals for same :

 

module fir_q1#(parameter width=16
)(
input clk,
input signed [width-1:0]x,
input [2:0] addr,
input write_en,
output reg signed [width-1:0] x_out,
output reg signed [31:0] out
);
reg [width-1:0] flipflop [4:0];
reg signed [15:0] coff [0:5];
integer i;
initial
begin
$readmemb ("memoryh.mem",coff);
for (i=0;i<6;i=i+1)
begin
$display("value in mem at i %0d",coff[i]);
end
end

 

//inferring a block ram

always @(posedge clk)
begin
if(write_en)
begin
coff[addr] <= x;
end
else
begin
x_out <= coff[addr];
end
end

always@(posedge clk )
begin
out<=x*coff[0]+flipflop[0]*coff[1]+flipflop[1]*coff[2]+flipflop[2]*coff[3]+flipflop[3]*coff[4]+flipflop[4]*coff[5];
flipflop[0]<=x;
flipflop[1]<=flipflop[0];
flipflop[2]<=flipflop[1];
flipflop[3]<=flipflop[2];
flipflop[4]<=flipflop[3];
end
endmodule

 

Also I am assuming your "out" port is supposed to be a flop(as you have declared it reg). So its a good practice to use nonblocking instead of blocking assignments for them.

 

Regards,

Ninad

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4 Replies
u4223374
Advisor
Advisor
1,109 Views
Registered: ‎04-26-2015

I think it's all from the first warning. That means that it's failing to initialize coff. Since coff isn't initialized (might as well be initialized to zero), all the flipflop values are being multiplied by zero, so they can be optimized away, so x is never used...

 

There are a bunch of questions (and answers) on Google about fixing the readmemb error, so I suggest looking through those.

1,005 Views
Registered: ‎10-01-2019

I have checked values of coff using $display command. It prints out the values of coff which i have given in the file.

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nlotankar
Visitor
Visitor
991 Views
Registered: ‎11-14-2019

Hi,

The memory in your code infers to distributed RAM rather than block ram. This is causing issue while synthesizing.

Please take a look at below modified code to infer block RAM, I have added a few signals for same :

 

module fir_q1#(parameter width=16
)(
input clk,
input signed [width-1:0]x,
input [2:0] addr,
input write_en,
output reg signed [width-1:0] x_out,
output reg signed [31:0] out
);
reg [width-1:0] flipflop [4:0];
reg signed [15:0] coff [0:5];
integer i;
initial
begin
$readmemb ("memoryh.mem",coff);
for (i=0;i<6;i=i+1)
begin
$display("value in mem at i %0d",coff[i]);
end
end

 

//inferring a block ram

always @(posedge clk)
begin
if(write_en)
begin
coff[addr] <= x;
end
else
begin
x_out <= coff[addr];
end
end

always@(posedge clk )
begin
out<=x*coff[0]+flipflop[0]*coff[1]+flipflop[1]*coff[2]+flipflop[2]*coff[3]+flipflop[3]*coff[4]+flipflop[4]*coff[5];
flipflop[0]<=x;
flipflop[1]<=flipflop[0];
flipflop[2]<=flipflop[1];
flipflop[3]<=flipflop[2];
flipflop[4]<=flipflop[3];
end
endmodule

 

Also I am assuming your "out" port is supposed to be a flop(as you have declared it reg). So its a good practice to use nonblocking instead of blocking assignments for them.

 

Regards,

Ninad

View solution in original post

983 Views
Registered: ‎10-01-2019

Thank you @nlotankar .

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