07-01-2019 09:39 PM
I created my design in Vivado 2017.4 Version and now I want to transfer it to 2018.3 version, while synthesis I got an error stating " [Synth 8-3493] module does not have matching formal port for component port. "
Could you please tell why does this error come although my design was perfectly working in the 2017.8 version.
07-02-2019 01:46 AM
07-02-2019 07:47 PM
If the module mentioned is not from a Xilinx IP, you need to check if the port mapping in the module instantiation matches the component declaration.