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Observer frivera
Observer
7,935 Views
Registered: ‎02-23-2016

WARNING: [Synth 8-3331] design XXX has unconnected port YYY

I am working in a project that has 10 modules, including the top design and three IP modules (2 FFT and 1 Complex Multiplier). The problem I have is that I am receiving a lot of Synth 8-3331 warnings and several modules are left out in the synthesis phase. I have checked the signals involved and all of them are instantiated, declared and initialized correctly. The RTL schematic obtained is correct; the problem is the synthesis schematic that leave a lot of signals unconnected and no explanation is given. I have a lot of time working in this design making a lot of different alternatives but I have not get a solution. I would appreciate some guidance with this problem. How can I have more detail about this warning and understand why Vivado is delivering that message?. Do I have to send my complete design? I am enclosing a copy of the Vivado Synthesis Report. I will appreciate any comment.

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8 Replies
Xilinx Employee
Xilinx Employee
7,920 Views
Registered: ‎08-01-2008

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

you can ignore these warnings safely . i can 0 error an 0 critical warnings so its good to go for implementation .
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
7,912 Views
Registered: ‎10-24-2013

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

Hi @frivera

Did you verify the functionality of the design by running post synthesis simulation?

If that is verified, you can safely ignore these warnings. You may want to review why you have unconnected ports in your design by opening the synthesized design.

 

Thanks,Vijay
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Moderator
Moderator
7,893 Views
Registered: ‎07-21-2014

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

@frivera

 

This warning was generated by the tool to make you aware about the module port connections, if these connections(unconnected ports) are valid as per your design then you can safely ignore them.

 

Thanks,
Anusheel
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Observer frivera
Observer
7,863 Views
Registered: ‎02-23-2016

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

Thanks guys for the answers. As I said in my message there are internal unconnected ports (I know now that I can safely ignore them) but also unconnected ports that belong to my design and affect its functionality. My design has a FMS (Finite State Machine) originally with one always block. I changed it to a 3 always block structure (I read and applied a very good paper from a guy called Clifford E. Cummings about the best way to design FMS in SystemVerilog) and the unconnected ports of my design were eliminated. I still have some but are due to design problem that I already detected. Once I did the change a new problem appeared. The synthesis process hung and never ended; I am using Vivado 2016-2. I run exactly the same design in Vivado 2016-1 and everything worked OK. So the end of this story is that Vivado 2016-2 is not working properly. I will continue with my design with Vivado 2016-1 and waiting for a new release.

 

Thanks and Regards,

Francisco

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Observer frivera
Observer
7,513 Views
Registered: ‎02-23-2016

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

Sorry for the time of this answer but I was out for a while. I have gone further with my design but I still have unconnected port in my synthesis design. My RTL schematic is ok now (all design modules are included) and I can run a behavioral simulation using a simple testbench I developed. The synthesis and implementation processes get a lot of warnings but no error messages. I am enclosing the Synthesis Report; I tried to include the Archive Project file but is too big so I just wondering if you have a FTP server for sending the file. I would like to understand (and get the solution of) the following WARNING and INFO obtained (I am including samples only):

 

WARNING: [filemgmt 56-147] Overwrite of existing file isn't enabled. Please specify -force to overwrite file ...

WARNING: [Synth 8-3331] design led_decoder has unconnected port out_ifft_re[0][15] ...

WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'cmpy_0' instantiated as 'Complex_Mult_IP' ...

WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'xfft_0' instantiated as 'FFT_Mod_IP' ...

WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'xfft_1' instantiated as 'IFFT_Mod_IP' ...

INFO: [Synth 8-4471] merging register 'data_table_re_reg[31][7:-7]' into 'data_table_re_reg[6][7:-7]' ...

INFO: [Synth 8-3886] merging instance 'CONTRi_0/out_ifft_im_reg[244][1]' (FDRE) to 'CONTRi_0/out_ifft_re_reg[244][1]' ...

 

The synthesis schematic obtained leaves out the input (Data_Input_CORR) and output (led_decoder) modules and there are no messages about. There is a big difference between the RTL schematic and the synthesis schematic obtained.

I will appreciate any comment.

 

Thanks and regards,

Francisco

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Observer frivera
Observer
7,430 Views
Registered: ‎02-23-2016

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

I am still waiting for some comments to my message posted on September 25th. In the meantime I have used the attributes KEEP, DONT_TOUCH and KEEP_HIERARCHY. After using these attributes the synthesis schematic improved and the unconnected port appeared but the synthesis messages continue and the post-synthesis functional simulation does not work. I have two types of messages that affect my design:

[Synth 8-3331] design led_decoder has unconnected port out_ifft_re[0][15], and

[Synth 8-3332] Sequential element (data_table_re_reg[0][7]) is unused and will be removed from module Data_Input_CORR__1.

The first message means the tool is not considering the signals that feed the output module (led_decoder) and the second message indicate that the tool is not considering the inputs generated in the input module (Data_Input_CORR).

The problem is that there is not explanation of why Vivado is doing that. I have no problem with the Behavioral Functional simulation; it works OK.

I will appreciate any comment.

Thanks,

Francisco

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Visitor katkinson
Visitor
2,604 Views
Registered: ‎03-07-2018

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

We're having very similar issues. Did you ever find a solution to this?

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Moderator
Moderator
2,478 Views
Registered: ‎07-21-2014

Re: WARNING: [Synth 8-3331] design XXX has unconnected port YYY

@katkinson

 

Such issues are design dependent. Can you please start a new thread with the synthesis log file and snapshot of your netlist schematic? 

 

Thanks,

Anusheel

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