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Observer rmogster
Observer
3,133 Views
Registered: ‎12-12-2017

WARNING: [Timing 38-316]

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I am getting several "WARNING: [Timing 38-316]"  messages when I compile the current design.

I have one file that gives the following warning:

 

WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'regs_0/rd_slot_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.

 

I tracked this down to the following line in the xdc file.

create_clock -period 100.0 -name s_axis_aclk [get_ports s_axis_aclk]

 

This is where it is a problem.  The Vivado tool claims the XDC file is inside the XCIX file, which is an encrypted file.

 

How do I convince the tool to let me change the clock period from 100.0 to 5.0 ?

Also, how do I get the tool to generate all the XDC files where I can get at them?

 

Thanks.

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Moderator
Moderator
3,865 Views
Registered: ‎03-16-2017

Re: WARNING: [Timing 38-316]

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Hi @rmogster

 

You can safely ignore this warning. 

 

The warning is saying that the IP OOC synthesis is running with clock constrained to 100 ns whereas during top level synthesis and implementation the clock is constrained to 5 ns. 

 

Here you will see _ooc.xdc file is only read during IP OOC synthesis whereas normal IP XDC is read in tol level synthesis and implementation. 

 

For your reference, you can have a look into this thread.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
4 Replies
Moderator
Moderator
3,866 Views
Registered: ‎03-16-2017

Re: WARNING: [Timing 38-316]

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Hi @rmogster

 

You can safely ignore this warning. 

 

The warning is saying that the IP OOC synthesis is running with clock constrained to 100 ns whereas during top level synthesis and implementation the clock is constrained to 5 ns. 

 

Here you will see _ooc.xdc file is only read during IP OOC synthesis whereas normal IP XDC is read in tol level synthesis and implementation. 

 

For your reference, you can have a look into this thread.

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Moderator
Moderator
3,091 Views
Registered: ‎09-15-2016

Re: WARNING: [Timing 38-316]

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Hi @rmogster

 

Warning says that IP will be synthesized with different clock period if run with global synthesis than the ooc mode. Since you are using ooc mode, you can change the desired target frequency as mentioned in the below link, page 41:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug896-vivado-ip.pdf

 

XCIX is a binary file which you can add as source in Vivado GUI like XCI file. Refer the above link onlyl for more information on this.

 

Regards

Rohit

Regards
Rohit
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3,074 Views
Registered: ‎01-22-2015

Re: WARNING: [Timing 38-316]

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@rmogster

 

The underlying issue is that synthesis is “timing driven”. That is, synthesis uses clock frequency to do things that can later help implementation pass timing analysis.

 

When you use Global synthesis (instead of OOC synthesis) for your IP then synthesis automatically gets clock frequency from the clock modules in your project.  However, OOC synthesis is done separate from your project and without knowledge of the clocks used in your project.  Hence, for OOC synthesis of IP, you must manually enter clock frequency -- or -- let OOC synthesis simply guess at the frequency.  If project-synthesis later finds that OOC-synthesis used the wrong clock frequency then you get the 38-316 warning.

 

In your project, you will find a file for your IP that ends with “_ooc.xdc”.  This text-file is called the OOC-constraints file for your IP.  Inside this file you will find a create_clock constraint that specifies the clock period/frequency used during OOC synthesis.  Unfortunately, you cannot simply edit the constraint and change the clock period because the file is read-only. 

 

Sometimes, you can enter a clock frequency for OOC synthesis during setup of the IP.   However, this is not the case for your FIFO IP.   So, you can follow the recommendation of @thakurr and use the method outlined in ug896 “Setting the Target Clock Period”.

 

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Moderator
Moderator
3,022 Views
Registered: ‎09-15-2016

Re: WARNING: [Timing 38-316]

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@rmogster

 

If your issue is resolved  then please close the thread by marking the helpful post as accepted solution. This will help users incurring same issue in future.

 

Regards

Rohit

Regards
Rohit
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