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Visitor
Visitor
6,169 Views
Registered: ‎08-21-2009

WebPack and multi-source problem... [VHDL]

 

 I have such code:
"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
  Port
  (
  clk1 : in STD_LOGIC;
  clk2 : in STD_LOGIC;
  data1 : inout STD_LOGIC_VECTOR (7 downto 0);
  data2 : inout STD_LOGIC_VECTOR (7 downto 0)
  );
end main;

architecture Behavioral of main is
type bit8_ur is array (7 downto 0) of std_logic;
type bit8_uca is array (natural range <>) of bit8_ur;

function bit8_resolve(v : bit8_uca) return bit8_ur is
variable res : bit8_ur;
begin
 if (v'LENGTH = 0) then return X"00"; end if;
 res := "ZZZZZZZZ";
 for i in v'range loop
  if (v(i) /= "ZZZZZZZZ") then
  res := v(i);
  end if;
 end loop;
 return res;
end function bit8_resolve;

subtype bit8_r is bit8_resolve bit8_ur;

signal idata1 : bit8_r := X"00";
signal idata2 : bit8_r := X"00";

function BIT8_R_TO_STD_LOGIC_VECTOR8(arg : bit8_r) return std_logic_vector is
variable res : std_logic_vector(7 downto 0) := X"00";
begin
 for i in arg'RANGE loop
  res(i) := arg(i);
 end loop;

 return res;
end function BIT8_R_TO_STD_LOGIC_VECTOR8;

begin

 data1 <= BIT8_R_TO_STD_LOGIC_VECTOR8(idata1);
 data2 <= BIT8_R_TO_STD_LOGIC_VECTOR8(idata2);

 RE : process (clk1)
 begin
  if ( rising_edge(clk1) ) then
  idata1 <= X"11";
  idata2 <= X"22";  
  else
  idata1 <= "ZZZZZZZZ";
  idata2 <= "ZZZZZZZZ";
  end if;
 end process RE;
 
 
 FE : process (clk2)
 begin
  if (falling_edge(clk2)) then
  idata1 <= X"99";
  idata2 <= X"88";
  else
  idata1 <= "ZZZZZZZZ";
  idata2 <= "ZZZZZZZZ";
  end if;
 end process FE;
end Behavioral;


Seems simple, right ?
And it is... when clk1 has rising edge, post 11 and 22 to lines data1, data2. When clk2 has falling edge, post 99, 88 to lines. And clk2 has higher priority because of structure of resolve function. And I got error:
ERROR:Xst:827 - "E:/PROJECTS/FPGA/WebISE 11/FSMtest1/main.vhd" line 93: Signal idata1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
Beautiful, isn't it ? I tried to make opposite edges in this if, make dependency of opposite clock (for if (clk2...) use clk1 when is 0 for example) and nothing... still errors...
But let's make some changes: comment in both "ifs"  part in the else, so it would look like:
  if (falling_edge(clk2)) then
  idata1 <= X"99";
  idata2 <= X"88";
  --else
  --idata1 <= "ZZZZZZZZ";
  --idata2 <= "ZZZZZZZZ";
  end if;

Do the same for second if... and now I get error:
ERROR:Xst:528 - Multi-source in Unit <main> on signal <N0>; this signal is connected to multiple drivers.
Drivers are: 
  Signal <N0> in Unit <main> is assigned to GND
  Signal <N1> in Unit <main> is assigned to VCC

This is the most beautiful.
Ok, I am newbie, so such errors just shoot me and I have no idea what to do. I hope that some of You know webISE well and can me help.
When I was beginning (still I am) I thought that writing VHDL code is enough - now I see, that code must be written in specific way for synthesize tool and I do not know this "specific ways" :/

Please help.

Best regards,
wrealcon.

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3 Replies
Highlighted
Historian
Historian
6,155 Views
Registered: ‎02-25-2008

Re: WebPack and multi-source problem... [VHDL]

Your problem is that you're trying to synthesize flip-flops which are sensitive to both edges of the clock.

 

You get the "bad synchronous description" error because those flip-flops do not exist in the Xilinx architecture. One way to deal with this is to use a DCM to double the clock and fake the two-edge flip-flop.

 

Your second failure comes about trying to drive the same signals from more than one process. This will result in a "multiple drivers" error.

 

The third failure is the result of assuming that the FPGA architecture has internal tri-states. Some much older Xilinx parts did have such internal tri-states but modern devices do not. Assigning 'Z' to an internal signal will result in a synthesis complaint.

 

-a

----------------------------Yes, I do this for a living.
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Visitor
Visitor
6,147 Views
Registered: ‎08-21-2009

Re: WebPack and multi-source problem... [VHDL]

 

Thank You for answer, bassman59.

As I have written before, I am huge beginner so I will have to search about DCM...

About second failure, I know that when I try to drive the same signal from more than one process, I will receive "multiple drivers" error. But what happened with resolution functions. Even if I will write that, I am able to get such error ! Why ??

About assigning Z to the signal - so how should I create for example bus or something what is inout for component when I cannot use Z state ? In real circuits chips must have tri-state bus to be able to connect more chips to the same bus. Why this rule does not apply to modern Xilinx devices ?

Is Spartan 3 modern device ?
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Historian
Historian
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Registered: ‎02-25-2008

Re: WebPack and multi-source problem... [VHDL]


wrealcon wrote:

 

Thank You for answer, bassman59.

As I have written before, I am huge beginner so I will have to search about DCM...


So do you truly understand why you cannot use both edges of the clock for the same flop?

 


About second failure, I know that when I try to drive the same signal from more than one process, I will receive "multiple drivers" error. But what happened with resolution functions. Even if I will write that, I am able to get such error ! Why ??

You need to go out and purchase a copy of Ashenden's "Designer's Guide to VHDL." As in -- right now.

 

The first thing you must understand is that std_logic and std_logic_vector are already resolved types -- a resolution function is NOT necessary. (This is why we use std_logic in the first place!)

 

Next, you must understand that even though the logic type is resolved, if one process drives a signal to '1' and another drives it to '0', what is the final outcome? THINK HARDWARE. In real hardware, you're likely to release the magic smoke if you do this. ModelSim kindly presents the result as a red 'X' -- and that red 'X' comes right out of the resolution table.



About assigning Z to the signal - so how should I create for example bus or something what is inout for component when I cannot use Z state ? In real circuits chips must have tri-state bus to be able to connect more chips to the same bus. Why this rule does not apply to modern Xilinx devices ?

Is Spartan 3 modern device ?

Of course you can assign 'Z' to a signal. But you should follow the rules laid it in the synthesis guide. First and foremost, the signal must be a port pin. It cannot be an internal net. (As I noted, tristatable lines are not in any recent Xilinx device -- I think the old XC4000 series from over ten years ago was the last to have them.)

 

Next -- the correct way to build a tristate output (as detailed in the most-wonderful XST guide) is:

 

    port_io <= Something when enable = '1' else 'Z';

 

Note that you must drive the signal enable at the appropriate time. If you turn on your output at the same time as the external device enables its output, you will still have bus contention (a big red 'X' in simulation and a puff of smoke in real life).

 

Of course port_io is readable:

 

    internal_sig <= port_io;

 

 The assumption, of course, is that you read port_io only when the external device drives the bus. How you do this depends entirely on your design.

 

----------------------------Yes, I do this for a living.
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