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Adventurer
Adventurer
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Registered: ‎07-17-2017

Weird warning for my design

Dear all.

 

Im currently synthesizing a design using Xilinx ISE.

Based on the warning below, it says that ALL the sub module is unconnected.

 

WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block <pe_block[0].pe.pe0>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block <pe_block[0].pe.pe0>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block <pe_block[0].pe.pe0>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block <pe_block[0].pe.pe0>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block <pe_block[1].pe.pe1>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block <pe_block[1].pe.pe1>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block <pe_block[1].pe.pe1>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block <pe_block[1].pe.pe1>.
It will be removed from the design.

 

WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaH> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaIx> of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaV> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaH> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaIx> of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaV> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/A/CompInterA> of block <Sync_Rst_CompInter> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/A/CompInterA> of block <Sync_Rst_CompInter> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaIy/DeltaLeftSubtract> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaIy/DeltaLeftSubtract> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.

 

This the verilog code for the top module that I currently synthesis.

 

module SystolicArrayNovelty2(Clk,Rst,SubSec,QueSec,PDeltaH,PreDeltaIy,SubSecOut);

    parameter ComputeDataWidth        = 8;
    parameter PE = 2; //LENGTH
    parameter QC = 2; //QC bit size
    
    input                                           Clk,Rst;
    input                                   [QC-1:0]  SubSec;
    input             wire              [(PE*QC)-1:0]  QueSec;
    input                        [ComputeDataWidth-1:0]     PreDeltaH,PreDeltaIy;
    output                                 [QC-1:0]     SubSecOut;

    wire                    [ComputeDataWidth-1:0] h         [PE-1:0];
    wire                    [ComputeDataWidth-1:0] l         [PE-1:0];
   wire                                [PE*3-1:0] SSout;    
    
    genvar i;

    generate
        for (i=0; i < PE; i = i + 1)
            begin : pe_block
                if (i == 0)                       //first processing element in auto-generated chain
                    begin:pe
                        ProcessingElementNovelty2 pe0
                            (  .Clk                       (Clk),
                                .Rst                       (Rst),
                        .SS                        (SubSec[1:0]),
                        .QC                        (QueSec[1:0]),
                            .PreDeltaH                 (PDeltaH),
                        .PreDeltaIy                (PreDeltaIy),
                                .DelH                      (h[i]),
                        .DelIy                     (l[i]),
                                .SS_Out                    (SSout[1:0])
                       );  
                    end
                else         //processing elements other than first one
                    begin:pe
                  ProcessingElementNovelty2 pe1
                            (   .Clk                       (Clk),
                                 .Rst                       (Rst),
                         .SS                        (SSout[(2*i)-1:(2*i)-2]),
                         .QC                        (QueSec[(2*i)+1:(2*i)]),
                             .PreDeltaH                 (h[i-1]),
                         .PreDeltaIy                (l[i-1]),
                                 .DelH                      (h[i]),
                         .DelIy                     (l[i]),
                                 .SS_Out                    (SubSecOut)
                           );
                    end
            end
    endgenerate
endmodule

 

AND this the submodule verilog code based on the above top module and RTL diagram with no warning.

 

`timescale 1ns / 1ps
module ProcessingElementNovelty2(Clk,Rst,SS,QC,PreDeltaH,PreDeltaIy,
                                         DelH,DelIy,SS_Out);
    
    parameter ComputeDataWidth        = 8;
    
    localparam
    N_A         = 2'b00,        //nucleotide "A"
    N_C         = 2'b01,        //nucleotide "C"
    N_G         = 2'b10,        //nucleotide "G"
    N_T         = 2'b11;        //nucleotide "T"
    
   input                                           Clk,Rst;
    input                                       [1:0]  SS,QC;
   input             signed    [ComputeDataWidth-1:0]     PreDeltaH,PreDeltaIy;
    output          signed     [ComputeDataWidth-1:0]     DelH,DelIy;
   output                                       [1:0]  SS_Out;    
    
    wire           signed    [ComputeDataWidth-1:0] a,DelIx,DelV;
    
    IntermediateA
                #(    .ComputeDataWidth    (ComputeDataWidth))
    A        
                (    
                   .Rst                        (Rst),
                   .SUBJECT_SEQUENCE           (SS),
                   .QUERY_CHARACTER            (QC),
                    .DelIx_i_1_j                (DelIx),
                    .DelIy_i_j_1                (PreDeltaIy),
                    .SCORE_InterA               (a),
                    .SUBJECT_SEQUENCE_OUT       (SS_Out)
                );
                
    Sync_Rst_TWO_Input_Sub
                #(    .ComputeDataWidth    (ComputeDataWidth))
    DeltaH        
                (    
                    .Clk                         (Clk),                   
                    .Rst                     (Rst),
                   .A                              (a),
                    .B                              (DelV),
                    .AdditionOUT                 (DelH)
                );
                
    Sync_Rst_TWO_Input_Sub
                #(    .ComputeDataWidth    (ComputeDataWidth))
    DeltaV        
                (    
                    .Clk                         (Clk),                   
                    .Rst                     (Rst),
                   .A                              (a),
                    .B                              (PreDeltaH),
                    .AdditionOUT                 (DelV)
                );
                
    DelTop
                #(    .ComputeDataWidth    (ComputeDataWidth))
    DeltaIx    
                (    .Clk                        (Clk),
                   .Rst                        (Rst),
                    .InterA                         (a),
                    .PreDelH                       (PreDeltaH),
                    .SCORE_DelTop               (DelIx)
                );
                
    DelLeft
                #(    .ComputeDataWidth    (ComputeDataWidth))
    DeltaIy    
                (    
                    .Clk                        (Clk),
                   .Rst                        (Rst),
                    .InterA                         (a),
                   .PreDelIy_i_j_1             (PreDeltaIy),
                    .PreDelV                       (DelV),
                    .SCORE_DelLeft              (DelIy)
                );            
                
endmodule

 

2018-08-08_12-10-16.png

 

Can anyone help me?

 

Thank you very much.

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9 Replies
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Moderator
Moderator
1,274 Views
Registered: ‎03-16-2017

Hi @dayana42200,

 

Try to clean the project files and re-parse the files.

 

To cleanup project files, go to "Project" => "Cleanup Project Files..."

 

Share the generated log file if you are still facing the same issue.

 

Regards,

hemangd

 

Regards,
hemangd

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Adventurer
Adventurer
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Registered: ‎07-17-2017

Hello @hemangd

Ive cleanup a project files and its the same.
What is generated log file? (in what form) (what kind of .xxx files?)

Regards,
Dayana
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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @dayana42200,

 

Can you provide the archived project to regenerate these warnings at our end?

 

I have tried to regenerate it using provided codes but there are missing source files. Hence, please provide.

 

Regards,

hemangd

Regards,
hemangd

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Adventurer
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Registered: ‎07-17-2017

Hello @hemangd

 

Ok Ill attached all the source file

 

Regards,

 

Dayana.

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Adventurer
Adventurer
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Registered: ‎07-17-2017

@hemangd

 

Is the attached source working?

 

 

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @dayana42200,

 

Yes, i am able to reproduce the issue. 

 

We are working on it. Please give us some time.

 

Regards,

hemangd

Regards,
hemangd

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Adventurer
Adventurer
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Registered: ‎07-17-2017

@hemangd

 

Alright. Thank you very much.

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Adventurer
Adventurer
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Registered: ‎07-17-2017

@hemangd

 

Do you now why is this happen?

As the can see the ports at the top module (SystolicArrayNovelty2) are connected expect for the output at one of the sub module (ProcessingElementNovelty2) which I intentionally did not connect it.

 

 

2018-08-13_16-26-25.jpg

 

When click the submodule, most of the blocks are remove. It shouldnt be remove as the some the the ports are internally connected within the submodule and not relate the the ports of the top module.

 

Also the submodule ports are all connected (figure shown earlier at the top post)

 

2018-08-13_16-27-33.jpg

 

Thank you.

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Adventurer
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Registered: ‎07-17-2017

@hemangd

 

I also tried to used other compiler but it is connected (see attachment).

 

2018-08-22_9-32-02.jpg

 

2018-08-22_9-28-39.jpg

 

Maybe Xilinx iSE 14.7 have problem?

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