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Teacher rcingham
Teacher
11,811 Views
Registered: ‎09-09-2010

What are advantages of XCF file during synthesis?

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I'm rejigging an established design, and I have had a problem relating to the .XCF file that XST was reading when the [Process > Properties > Synthesis Options > Use Synthesis Constraints File] option was set. I reckon I know how to sort it, but I was wondering how advantageous it was likely to be to have this option set.


So I looked in UG627, which told me how to set the option in ISE or on the command line. Then I looked in UG626, which didn't seem to mention it. And a search on this forum - and indeed the rest of the Xilinx web-site - didn't find anything obviously useful.


Would a guru like to enlighten me? Or point me at a document the explains when it is worth doing, and when it probably makes little difference?

 

ISE 12.3 for Virtex-5 devices, BTW.


TIA!



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"If it don't work in simulation, it won't work on the board."
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Teacher rcingham
Teacher
9,175 Views
Registered: ‎09-09-2010

Re: What are advantages of XCF file during synthesis?

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As alluded to in this thread, I can finally answer my question.

 

By fiddling with the clock PERIOD constraints (halving one of them) in the XCF, and also selecting a 'good' value of Starting Placer Cost Table in Map, I got a design previously done by persons long gone to meet Timing Closure without changing that design, and so adding the technical risk of inadequate validation.

 


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"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
11,795 Views
Registered: ‎04-06-2010

Re: What are advantages of XCF file during synthesis?

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Applying constraints in the XCF will make your code more portable rather than in the code.

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Teacher rcingham
Teacher
11,786 Views
Registered: ‎09-09-2010

Re: What are advantages of XCF file during synthesis?

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Actually, my question was more on the lines of
"Why give constraints to XST from a XCF file when they are all already in a UCF that Translate reads?"

 


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"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
11,783 Views
Registered: ‎05-14-2008

Re: What are advantages of XCF file during synthesis?

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"Why give constraints to XST from a XCF file when they are all already in a UCF that Translate reads?"

 

This brings "timing-driven Synthesis". Timing constraints in XCF will help XST produce a netlist of better timing performance.

 

-Vivian

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Teacher rcingham
Teacher
11,780 Views
Registered: ‎09-09-2010

Re: What are advantages of XCF file during synthesis?

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Sounds sensible.

So, should I move all possible timing-related constraints from the UCF into the XCF that XST reads?

And is any of this documented somewhere?

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"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
11,780 Views
Registered: ‎04-06-2010

Re: What are advantages of XCF file during synthesis?

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Vivian is correct.  But I would like more clarification from you.  When you say "constraints" are you referring to just "timing constraints"?   

 

If you're simply referring to timing constraints, then Vivian's answer is fully correct.

 

However, if you're referring to other constraints, like our KEEP constraint.  Then adding it to the XCF would prevent XST from removing it. If you add a KEEP constraint in the UCF, the instance may have already been removed by XST; which would make NGDBuild error out.

 

Hope this helps...

 

 

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Teacher rcingham
Teacher
11,768 Views
Registered: ‎09-09-2010

Re: What are advantages of XCF file during synthesis?

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The UCF contains pin-related constraints and some timing-related constraints. I have KEEP attributes in the HDL.

We are very unlikely to change FPGA vendor in the forseeable future, so 'portability' is not an issue. I'd be happy to put all constraints in the HDL, but the tools don't support this.

I REALLY would like to read an Application Note or something on this!

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"If it don't work in simulation, it won't work on the board."
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Visitor 01121965
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Registered: ‎11-22-2011

Re: What are advantages of XCF file during synthesis?

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I can only agree with you. It is a rather confusing topic and the more you read about in the various documents, the more

it is unclear (at least to me). For example the "XST User Guide" (xst_v6s6.pdf on page 453) mentiones also the ucf-file as a source for specifying timing constraints. SInce this is the documenation of XST, I would conclude that the timing constraints

specified in the ucf-file are also used for the timing optimisation during synthesis.

 

@Xilinx: Please improve the the documenation here !

 

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Xilinx Employee
Xilinx Employee
11,647 Views
Registered: ‎05-14-2008

Re: What are advantages of XCF file during synthesis?

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@01121965 wrote:

I can only agree with you. It is a rather confusing topic and the more you read about in the various documents, the more

it is unclear (at least to me). For example the "XST User Guide" (xst_v6s6.pdf on page 453) mentiones also the ucf-file as a source for specifying timing constraints. SInce this is the documenation of XST, I would conclude that the timing constraints

specified in the ucf-file are also used for the timing optimisation during synthesis.

 

@Xilinx: Please improve the the documenation here !

 


Good catch! Thanks for the suggestion. I'll follow up this.

 

Vivian

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Observer beppe.eson
Observer
11,494 Views
Registered: ‎12-10-2010

Re: What are advantages of XCF file during synthesis?

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I didn't quite get it. Can you use the ucf-file as a source for specifying timing constraints for the synthesis? Phrased in another way, does XST read the ucf-file when synthesizing an HDL design?

/B

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Xilinx Employee
Xilinx Employee
6,355 Views
Registered: ‎05-14-2008

Re: What are advantages of XCF file during synthesis?

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XST does not read UCF. UCF is for post-Synthesis processes - Translate, MAP, PAR, but not Synthesis. Vivian
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Teacher rcingham
Teacher
9,176 Views
Registered: ‎09-09-2010

Re: What are advantages of XCF file during synthesis?

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As alluded to in this thread, I can finally answer my question.

 

By fiddling with the clock PERIOD constraints (halving one of them) in the XCF, and also selecting a 'good' value of Starting Placer Cost Table in Map, I got a design previously done by persons long gone to meet Timing Closure without changing that design, and so adding the technical risk of inadequate validation.

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor dafeldib
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4,914 Views
Registered: ‎03-05-2014

Re: What are advantages of XCF file during synthesis?

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Hi,

 

Yes, exactly this is why I used .xcf file (to prevent removing of duplicate instances). Now I want to run the processes from within an tcl script. I do create a project, add the .xcf file and .ucf file, but the synthesis process just ignores the constraints. How can I force it to take the .xcf into consideration using TCL script. Attached is my tcl script.

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Visitor dafeldib
Visitor
4,892 Views
Registered: ‎03-05-2014

Re: What are advantages of XCF file during synthesis?

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Got to know how to set the properties needed to use an .xcf file, namely:

 

#project set "Use Synthesis Constraints File" true
#project set "Synthesis Constraints File" constraints_file_name

 

However my ucf file is still ignored by the implementation process although I have added my .ucf file using xfile add

Are there any properties to be set such that the implementation process does not ignore my .ucf file?

 

Best Regards,

Dalia

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Xilinx Employee
Xilinx Employee
4,879 Views
Registered: ‎11-28-2007

Re: What are advantages of XCF file during synthesis?

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Hi Dalia,

 

for the XST .XCF constraints file, that cannot be set/added by the normal xfile add command. It's an option of XST:

 

project set "Synthesis Constraints File" "xxx.xcf"

 

 

 

Best regards,

Dries

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