01-30-2019 07:24 PM
I run into a harsh situation that I have a prototyping project which puts a CPU design in the xcvu440.
I used synplify_permier to synthesize the rtl to get a netlist.
Base on the same netlist, and also follow the same script to generate the two bit files in vivado.
The two bitfiles both have very good timing.
The problem is when I try to run Kernel on both of them, one kernel can be brought up everytime, and the other one fails everytime. (say I tried 30 times for the conclusion of everytime)
I had CDC design in this current rtl design. I wonder could it be possible that the CDC design is not done very well and lead to my current problem.
Do any one has any idea about how should I further look into this problem and hopefully find the cause ?
I do not have any idea what I could try to locate the problem basing on the fact that timing is pretty good and the netlist is the same.
Greatly appreciate for any contribution or any suggestions.
02-04-2019 01:36 PM
How did you specify the CDC?
Did you just false path it? Is it a FIFO? did you do safe CDC?
Do you have some false paths you're not supposed to.
02-04-2019 10:53 PM
>>When I try to run Kernel on both of them, one kernel can be brought up everytime, and the other one fails everytime.
What do you mean by this? Please elaborate.
Which Xilinx tool are you using?