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Adventurer
Adventurer
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Registered: ‎10-14-2017

What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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I'm implementing a design where I have a process which defines a variable of STD_LOGIC_VECTOR (7 downto 0). Now, due to the nature of this specific implementation (I'm trying to make the design more generic later on) the two lower bits are never used and so ISE will optimize those away. 

However, I have a signal which is driven by that variable and which is input into Xilinx IP core so this is signal is not optimized. My question is what will happen, when the variable is optimized, because it's index range should change accordingly I think. So ISE should throw an error about index range mismatch?

Below is the process that I was talking about. The phase_out_var variable is assigned to phase out signal which is input into CORDIC core. 

	process (CLK) is
		variable phase_unsigned						: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
		variable phase_signed						: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
		variable negative_range						: STD_LOGIC := '0';
		variable phase_out_var						: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
		constant pi_value								: STD_LOGIC_VECTOR (7 downto 0) := "01100100";
		constant pi_value_negative					: unsigned (7 downto 0) := "10011100";
	begin
		if (rising_edge(CLK)) then
			if (s_axis_phase_tready = '1') then
				-- add the phase resolution to forward the signal in time
				phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + phase_resolution);
				
				-- check if PI range has been exceeded; if it has, then subtract PI (add negative PI) and change the sign
				if (phase_unsigned >= pi_value) then
					phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + pi_value_negative);
					negative_range := not negative_range;
				end if;
				
				-- convert from 0...2PI range to -PI...PI range
				case negative_range is
					when '0' => 
						phase_out_var :=  std_logic_vector(unsigned(phase_unsigned) + pi_value_negative);  -- move down to zero
					when '1' =>
						phase_out_var :=  phase_unsigned; -- move up from zero
					when others =>
						report "Catch-all statement reached, error";
				end case;
			end if;
			phase_out <= phase_out_var;
		end if;
	end process;

 

When I synthesized the design, the ISE gives the following warnings:

 

Xst:1293 - FF/Latch <phase_unsigned_0> has a constant value of 0 in block <phase_gen>. This FF/Latch will be trimmed during the optimization process.
Xst:1896 - Due to other FF/Latch trimming, FF/Latch <phase_unsigned_1> has a constant value of 0 in block <phase_gen>. This FF/Latch will be trimmed during the optimization process.
Xst:1896 - Due to other FF/Latch trimming, FF/Latch <phase_out_var_0> has a constant value of 0 in block <phase_gen>. This FF/Latch will be trimmed during the optimization process.
Xst:1896 - Due to other FF/Latch trimming, FF/Latch <phase_out_var_1> has a constant value of 0 in block <phase_gen>. This FF/Latch will be trimmed during the optimization process.

 

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Accepted Solutions
368 Views
Registered: ‎01-22-2015

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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@ronnu

So many good questions!  I know you are just trying to understand how synthesis works. 

As @richardhead say, VHDL has rules and ISE/Vivado will help you follow the VHDL rules.  Ensuring that your VHDL follows these rules (as you have) should be your focus.  As you gain experience, you will understand how *some* of your VHDL becomes hardware (via synthesis) – and this is a good goal for you.  However, it is not necessary that you know how *all* of your VHDL becomes hardware.

   …but I'm just trying to figure what happens when variable of type STD_LOGIC_VECTOR gets trimmed.
You have written correct VHDL code for assigning values to the 8 bits of signal, phase_out.   This will occur regardless of any variable trimming done by synthesis.

   …Will it's index range change if two lower bits are removed?
You have written VHDL code that correctly uses the 8 bit variable, phase_out_var.  So, from the VHDL perspective, phase_out_var will always have 8-bits.  That’s all you need to worry about. 

VHDL variables are typically used to make code more readable and easy to understand (as you have done).   It may help you to know that your VHDL process can be written as shown below, without the use of phase_out_var – and if you initialize phase_out to (others => '0') when phase_out is declared.

    --equivalent code if you initialize phase_out to (others => '0') when phase_out is declared
process (CLK) is variable phase_unsigned : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); variable phase_signed : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); variable negative_range : STD_LOGIC := '0'; constant pi_value : STD_LOGIC_VECTOR (7 downto 0) := "01100100"; constant pi_value_negative : unsigned (7 downto 0) := "10011100"; begin if (rising_edge(CLK)) then if (s_axis_phase_tready = '1') then -- add the phase resolution to forward the signal in time phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + phase_resolution); -- check if PI range has been exceeded; if it has, then subtract PI (add negative PI) and change the sign if (phase_unsigned >= pi_value) then phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + pi_value_negative); negative_range := not negative_range; end if; -- convert from 0...2PI range to -PI...PI range case negative_range is when '0' => phase_out <= std_logic_vector(unsigned(phase_unsigned) + pi_value_negative); -- move down to zero when '1' => phase_out <= phase_unsigned; -- move up from zero when others => report "Catch-all statement reached, error"; end case; end if; end if; end process;

 

7 Replies
Scholar richardhead
Scholar
451 Views
Registered: ‎08-01-2012

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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I dont really understand what the problem is.

You dont show the declaration of  phase out. What exactly are you expecting to be a problem?

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417 Views
Registered: ‎01-22-2015

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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@ronnu

The short answer is:  The warnings DO NOT say that VHDL signal, phase_out, has been trimmed.  

That is, if you open your implemented design you will probably find that all 8 bits of phase_out are present as registers called phase_out_reg[i], i=0-to-7.   If you find this is true, then there will be no problems connecting phase_out to your CORDIC core.  The warnings DO say that VHDL variables have been trimmed.  However, determining why this is happening is often the road to madness 😊.

In my early FPGA days, I too tried to reason through all the warnings that Xilinx ISE/Vivado synthesis threw at me.  Many, many times I was sure that a synthesis-generated warning pointed to a mistake made by synthesis – but I was always wrong. 

So, over the years, I’ve come up with some guidelines for myself:

  • Xilinx synthesis is always right.
  • You must resolve synthesis critical-warnings and synthesis errors. However, ordinary synthesis warnings are not a big deal and can usually be safely ignored.
  • When writing VHDL, clarity and readability are the primary goals - and NOT reducing the number of synthesis warnings.
  • Use simulation as much as possible. If simulation shows a problem with the VHDL then (and only then) do I study the synthesis warnings for clues to the problem.

Cheers,
Mark

Adventurer
Adventurer
397 Views
Registered: ‎10-14-2017

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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I'm actually not sure if there is a problem. I just want to understand the warning and learn what happens in this case.

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Adventurer
Adventurer
394 Views
Registered: ‎10-14-2017

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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Yes, the signal phase_out hasn't been trimmed, because I didn't get a warning. That wasn't my concern. I actually am not sure if there is a problem in the design, but I'm just trying to figure what happens when variable of type STD_LOGIC_VECTOR gets trimmed. Will it's index range change if two lower bits are removed? And if so, then can I still assign that variable to a signal of STD_LOGIC_VECTOR type which does not have those bottom bits removed?

Thank you for the guideline notes, I'll try to keep them in mind in the future.

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Scholar richardhead
Scholar
382 Views
Registered: ‎08-01-2012

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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@ronnu

if stuff gets trimmed, it wont affect your code, and wont affect any subsequent assignments.

Remember that VHDL has rules, and works in a certain way. Synthesisors attempt to convert your code to their logic. But this does not have any effect on the code you originally wrote.

So if the code is written in a good style, compiles, and simulates correctly, the likelyhood is that it will work the same on hardware (assuming it met timing).

369 Views
Registered: ‎01-22-2015

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

Jump to solution

@ronnu

So many good questions!  I know you are just trying to understand how synthesis works. 

As @richardhead say, VHDL has rules and ISE/Vivado will help you follow the VHDL rules.  Ensuring that your VHDL follows these rules (as you have) should be your focus.  As you gain experience, you will understand how *some* of your VHDL becomes hardware (via synthesis) – and this is a good goal for you.  However, it is not necessary that you know how *all* of your VHDL becomes hardware.

   …but I'm just trying to figure what happens when variable of type STD_LOGIC_VECTOR gets trimmed.
You have written correct VHDL code for assigning values to the 8 bits of signal, phase_out.   This will occur regardless of any variable trimming done by synthesis.

   …Will it's index range change if two lower bits are removed?
You have written VHDL code that correctly uses the 8 bit variable, phase_out_var.  So, from the VHDL perspective, phase_out_var will always have 8-bits.  That’s all you need to worry about. 

VHDL variables are typically used to make code more readable and easy to understand (as you have done).   It may help you to know that your VHDL process can be written as shown below, without the use of phase_out_var – and if you initialize phase_out to (others => '0') when phase_out is declared.

    --equivalent code if you initialize phase_out to (others => '0') when phase_out is declared
process (CLK) is variable phase_unsigned : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); variable phase_signed : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); variable negative_range : STD_LOGIC := '0'; constant pi_value : STD_LOGIC_VECTOR (7 downto 0) := "01100100"; constant pi_value_negative : unsigned (7 downto 0) := "10011100"; begin if (rising_edge(CLK)) then if (s_axis_phase_tready = '1') then -- add the phase resolution to forward the signal in time phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + phase_resolution); -- check if PI range has been exceeded; if it has, then subtract PI (add negative PI) and change the sign if (phase_unsigned >= pi_value) then phase_unsigned := std_logic_vector(unsigned(phase_unsigned) + pi_value_negative); negative_range := not negative_range; end if; -- convert from 0...2PI range to -PI...PI range case negative_range is when '0' => phase_out <= std_logic_vector(unsigned(phase_unsigned) + pi_value_negative); -- move down to zero when '1' => phase_out <= phase_unsigned; -- move up from zero when others => report "Catch-all statement reached, error"; end case; end if; end if; end process;

 

Adventurer
Adventurer
340 Views
Registered: ‎10-14-2017

Re: What happens when signal is driven by trimmed STD_LOGIC_VECTOR variable?

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Thank you for explaining. I guess I need not bother with all the warnings in the future, escpecially when design simulates correctly and works. I'll try to keep you're guideline in mind in future designes.

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