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Visitor kaza.
Visitor
353 Views
Registered: ‎09-27-2019

When using "don't care" value Vivado doesn't recognize FSM.

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Hi,

I've got problem with FSM extraction of Mealy FSM (Vivado (2019.1)). When I use don't care value ("-") it doesn't infer the FSM. However, when I check possible value combinations, it recognizes FSM properly. Has anyone encountered such problem?

Below are two code examples (in attachment full code):

Example 1 (using don't care - FSM not recognized):

               when st0 =>
                if (x = "-0") then
                   y <= b"0";
                    next_state <= st0;
                elsif (...)

 

Example 2 (without don't care - FSM properly recognized):

             when st0 =>
                if (x = "00") or (x = "10") then
                   y <= b"0";
                    next_state <= st0;
               elsif (...)

 

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Scholar richardhead
Scholar
300 Views
Registered: ‎08-01-2012

Re: When using "don't care" value Vivado doesn't recognize FSM.

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This is likely because (x="-0") in VHDL is not as useful as you think it is. If you were to simulate this code, and x = "10", it wouldnt match, because the code is looking for an explicit dont care state '-' on x, and it is '1', so it doesnt match.

To get around this in VHDL 1993, there is a non-standard library called std_logic_misc that adds a std_match function. So you can write this to function as you expect (and should synthesise in vivado, and work in simulation:

if std_match(x, "-0") then

Otherwise, in VHDL2008, you can use matching equality operators.

if x ?= "-0" then

Vivado 2017.4 had a problem with these in inline code, hopefully its fixed in 2019.1

3 Replies
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Scholar richardhead
Scholar
301 Views
Registered: ‎08-01-2012

Re: When using "don't care" value Vivado doesn't recognize FSM.

Jump to solution

This is likely because (x="-0") in VHDL is not as useful as you think it is. If you were to simulate this code, and x = "10", it wouldnt match, because the code is looking for an explicit dont care state '-' on x, and it is '1', so it doesnt match.

To get around this in VHDL 1993, there is a non-standard library called std_logic_misc that adds a std_match function. So you can write this to function as you expect (and should synthesise in vivado, and work in simulation:

if std_match(x, "-0") then

Otherwise, in VHDL2008, you can use matching equality operators.

if x ?= "-0" then

Vivado 2017.4 had a problem with these in inline code, hopefully its fixed in 2019.1

Visitor kaza.
Visitor
286 Views
Registered: ‎09-27-2019

Re: When using "don't care" value Vivado doesn't recognize FSM.

Jump to solution

@richardhead 

Thank you! This worked for me:

                if (x ?= "-0") then (...)

The FSM is proprely recognized.


@richardhead wrote:
if std_match(x, "-0") then

Vivado 2017.4 had a problem with these in inline code, hopefully its fixed in 2019.1

Don't know what was your problem, but I had to change the source type to VHDL2008 in file properties, because there was a syntax error. I thought Vivado has been using VHDL2008 by default since version 2014.

 

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Scholar richardhead
Scholar
259 Views
Registered: ‎08-01-2012

Re: When using "don't care" value Vivado doesn't recognize FSM.

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Vivado has had poor 2008 support until 2018, and 2019.1 looks better.

What didnt work was the std_logic version where a std_logic was returned instead of a boolean. It would synthesise but would synthesise to 0 (when it should have been a compare):

signal x_eq_zero : std_logic;

x_eq_zero <= (x ?= 0);
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