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Explorer
2,349 Views
Registered: ‎07-10-2013

## Where Do Primitive Constants Come From?

When a primitive is explicitly instantiated, e.g., a LUT6_2, and constant values (0s and 1s) are applied to the primitive's inputs, where do the constant values come from?  Are they present "within" or near to the instantiated primitive?  Are fabric routing resources possibly utilized to implement connection to the specified constant values?

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Explorer
2,804 Views
Registered: ‎07-10-2013

Thanks to all above for the interesting information and discussion.

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Mentor
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Registered: ‎02-24-2014

The INIT constants are found in the Language Template window.   I reproduce the LUT6 constants in VHDL.

```   -- The following constants are defined to allow for
--   equation-based INIT specification for a LUT6.
constant I0 : BIT_VECTOR(63 downto 0) := X"AAAAAAAAAAAAAAAA";
constant I1 : BIT_VECTOR(63 downto 0) := X"CCCCCCCCCCCCCCCC";
constant I2 : BIT_VECTOR(63 downto 0) := X"F0F0F0F0F0F0F0F0";
constant I3 : BIT_VECTOR(63 downto 0) := X"FF00FF00FF00FF00";
constant I4 : BIT_VECTOR(63 downto 0) := X"FFFF0000FFFF0000";
constant I5 : BIT_VECTOR(63 downto 0) := X"FFFFFFFF00000000";

constant  some_calc : BIT_VECTOR(63 downto 0) :=  I0 xor I1 xor I2 and I3;```

For programming the LUT6_2 primitive,  it's a little tricky, since you have 2 outputs, with one depending on I5=0 and the other with I5 = 1.   This requires assembling two equations, and gluing them together with different values of I5.  i.e.

`constant  some_calc : BIT_VECTOR(63 downto 0) :=  I5 and (some equation) OR not I5 and ( equation 2 );begin LUT6_2_inst : LUT6_2     generic map (        INIT =>  some_calc ) -- Specify LUT Contents     port map (        O6 => O6, -- 6/5-LUT output (1-bit)        O5 => O5, -- 5-LUT output (1-bit)        I0 => I0, -- LUT input (1-bit)        I1 => I1, -- LUT input (1-bit)        I2 => I2, -- LUT input (1-bit)        I3 => I3, -- LUT input (1-bit)        I4 => I4, -- LUT input (1-bit)        I5 => I5 -- LUT input (1-bit) ); -- End of LUT6_2_inst instantiation `

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Explorer
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Registered: ‎07-10-2013

@jmcclusk

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Mentor
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Registered: ‎02-24-2014

More closely reading your question,  the answer is yes,  constant values applied to an input must be generated by another LUT typically.   This is a rare situation, since during "opt_design",  constants are propagated forward and eliminated from LUT inputs.

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Explorer
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Registered: ‎07-10-2013

@@jmcclusk,

If true, that would seem to be a circular situation.  How would the constant-producing LUT be able to produce constant-value outputs, without itself needing constant-level inputs?

FYI, the situation of interest is where primitives would be explicitly instantiated and would (presumably) remain as instantiated in the design, eg., a 6-input LUT with an explicitly-specified INIT (truth table) value, then feeding into a flipflop; nothing would (presumably) be optimized away or eliminated necessarily.

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Teacher
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Registered: ‎11-14-2011

My understanding is that a constant '0' (anywhere in the FPGA - explicitly designed in or a signal optimised to a constant during synthesis) is simply tied to the ground supply of the device. Similarly, a constant '1' is tied to the Core Vcc.

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"That which we must learn to do, we learn by doing." - Aristotle
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Explorer
2,276 Views
Registered: ‎07-10-2013

@ hgleamon1,

As queried in my original post, are the sources of the '0' and '1' constant signals/levels present "within" or near to the instantiated primitive?  Are fabric routing resources possibly utilized to implement connection to the specified constant values?

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Teacher
2,267 Views
Registered: ‎11-14-2011

The short answer is "I don't know" but, at a physical level, you'd have to consider what a primitive really is - just a bunch of transistors which most certainly have core Vcc and Vee present.

My guess, then, would be that constant 0 and 1 values are tied directly to the nearest core supply to that basic element, i.e. there is no meaningful routing resource used (but maybe @austin could clarify without giving any Xilinx specific info away).

My question to you would be, why does this matter?

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"That which we must learn to do, we learn by doing." - Aristotle
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Explorer
2,256 Views
Registered: ‎07-10-2013

Yes, hopefully a Xilinx support person can provide some insight.

The reason I am asking is that I'd like to know whether there is necessarily a signal routing advantage (less interconnect resources used) in supplying primitive inputs with constant values, compared with perhaps feeding the inputs from the outputs of other primitives.  In a situation in which a primitive has logically-unused inputs which need to receive pacifying values, it would be useful to know whether use of static 0 and 1 values is always necessarily the best way to go, from all possible points of view.

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Teacher
2,251 Views
Registered: ‎11-14-2011

My thoughts would be that if you supplied constant "pacifying" signals that never changed during run time, they would be optimised by the synthesiser to constant "tied" values which would use no routing, as I suggested.

In short: constant value with no requirement to change under run time - just tie it to '0' or '1'.

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"That which we must learn to do, we learn by doing." - Aristotle
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Scholar
1,817 Views
Registered: ‎02-27-2008

No,

The synthesis optimization will properly remove unused, redundant, never used logic.  Constant assignment and optimization is performed as much as it can be at synthesis.  Following synthesis, in implementation (place, route) optimizations continue.

So, the simple answer is, no, no matter how the RTL is written, the tools will do their utmost to reduce it to a design that fits, meets timing, and works as intended.

Viewing the elaborated design (elaboration may be done as part of synthesis and viewed) may shed some light on what happens at that step.  One may then view the synthesized result, and finally the implemented schematic.

The fiddly details of how we design our devices remains Xilinx intellectual property.  I advise you to read our over 4,000 patents if you are really curious how we actually create and use our devices and software tools.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Mentor
1,810 Views
Registered: ‎02-24-2014

I've looked into the question of where VCC and GND connections come from..    I opened up a VU065 Ultrascale design and looked for the VCC and GND nets.     There are a LOT of them, and it's not a continuous net, but hundreds of net segments, all over the place.    Every switchbox has a hard VCC and GND tiepoint.  The VCC is in the upper left, as the image below shows.

In the design I examined,  the GND tiepoints were never used, and GND signals were instead generated by LUT primitives with no inputs.   Why the VCC tiepoints are used, and not the GND tiepoints, is a complete mystery.   Some GND signals were generated by VCC running through an inverter on a slice input.   These GND and VCC signals definitely use up routing resources, so they don't come for free.

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Scholar
1,808 Views
Registered: ‎02-27-2008

All views are 'cartoons' -- a software view of the actual internal connections.

They do not reflect any actual points.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
2,805 Views
Registered: ‎07-10-2013

Thanks to all above for the interesting information and discussion.