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Observer chandima7
Observer
4,529 Views
Registered: ‎03-20-2009

Why can't use wire for continuous assignment?

Hi,

In my program I used a 32 bit wire to get the value and store it in a reg. Compilation is successful but in the synthesis it gives a error

 

"FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover.  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Synthesis" failed
ERROR: Unable to launch the RTL Schematic process. The input NGR file
 cannot be found. Please rerun the "Synthesize - XST" process after setting
 the property "Generate RTL Schematic" to Yes or Only. This property can be
 found under the Synthesis Options category."

 

code is as below. Please can any one help me on this? Thnks.

 

 

 module Tag_Seperator(clk,reset,tag_finish,data_out_TS);

output tag_finish        ;    //Reset a flag to indicate a tag or value
output [7:0]data_out_TS    ;    //8-bit data output
input clk,reset            ;        

reg  [7:0]data_out_TS;
reg tag_finish;
reg count;                    //Byte count in a word
parameter SET = 0;            //SET is set to zero, according to the upper level module requirement

    wire [31:0] data_out;
    reg deq;
    
    FIFO_Controller FC(clk, reset, data_in, enq, data_out, deq);
    
    initial
        begin
            assign deq = 1;        //Set to, initiate the FIFO read
            assign count = 0;
        end
        
        always @(posedge clk) begin   

            if(deq == 1) begin
                assign deq =0;
                
                if(count <= 3) begin                    
                      if(tag_finish == SET) begin           

                            tag_finish = ~SET;
                        end    
                    
                   case(count)
                        0:
                            data_out_TS <= data_out[7: 0];
                        1:
                            data_out_TS <= data_out[15: 8];
                        2:
                            data_out_TS <= data_out[23: 16];
                        3:
                            data_out_TS <= data_out[31: 24];
                    endcase                
            
                        if(data_out_TS == 8'b00000001) begin        //Set the flag when the delimiter is found
                            tag_finish = SET;
                        end    
                        
                            count = count + 1;
                end
                else begin
                    count = 0;                            
                    deq = 1;                            //deq is set to get the next FIFO output
                end
            end
        end        
endmodule

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2 Replies
Voyager
Voyager
4,515 Views
Registered: ‎08-30-2007

Re: Why can't use wire for continuous assignment?

I think you have multiple problems in your design that you need to address.

 

a) if you intend to synthesize, you should not ne using an initial statement.

b) wires cannot be used in the  procedural block - you need to use a reg type.

c) the varilable "count" is a single bit, but you treat it as if it can hold values up to 3.

 

Have you tried simulating your design?  If not, you're heading down a very sad path.

Simulation is your best friend when doing digital design.

 

Good luck

 

John Providenza

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Historian
Historian
4,508 Views
Registered: ‎02-25-2008

Re: Why can't use wire for continuous assignment?

You need to buy and study a good Verilog book. Palnitkar's is fine.

 

-a

----------------------------Yes, I do this for a living.
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