03-20-2009 12:29 AM
In my program I used a 32 bit wire to get the value and store it in a reg. Compilation is successful but in the synthesis it gives a error
"FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Process "Synthesis" failed
ERROR: Unable to launch the RTL Schematic process. The input NGR file
cannot be found. Please rerun the "Synthesize - XST" process after setting
the property "Generate RTL Schematic" to Yes or Only. This property can be
found under the Synthesis Options category."
code is as below. Please can any one help me on this? Thnks.
output tag_finish ; //Reset a flag to indicate a tag or value
output [7:0]data_out_TS ; //8-bit data output
input clk,reset ;
reg count; //Byte count in a word
parameter SET = 0; //SET is set to zero, according to the upper level module requirement
wire [31:0] data_out;
FIFO_Controller FC(clk, reset, data_in, enq, data_out, deq);
assign deq = 1; //Set to, initiate the FIFO read
assign count = 0;
always @(posedge clk) begin
if(deq == 1) begin
assign deq =0;
if(count <= 3) begin
if(tag_finish == SET) begin
tag_finish = ~SET;
data_out_TS <= data_out[7: 0];
data_out_TS <= data_out[15: 8];
data_out_TS <= data_out[23: 16];
data_out_TS <= data_out[31: 24];
if(data_out_TS == 8'b00000001) begin //Set the flag when the delimiter is found
tag_finish = SET;
count = count + 1;
count = 0;
deq = 1; //deq is set to get the next FIFO output
03-20-2009 08:38 AM
I think you have multiple problems in your design that you need to address.
a) if you intend to synthesize, you should not ne using an initial statement.
b) wires cannot be used in the procedural block - you need to use a reg type.
c) the varilable "count" is a single bit, but you treat it as if it can hold values up to 3.
Have you tried simulating your design? If not, you're heading down a very sad path.
Simulation is your best friend when doing digital design.
03-20-2009 09:58 AM
You need to buy and study a good Verilog book. Palnitkar's is fine.