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paebbels
Explorer
Explorer
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Registered: ‎04-24-2014

Why does UG 901 (Vivado Synthesis Guide) use the non standard conform VHDL packages?

The latest Vivado synthesis guide (UG901, 2017.2) still promotes the usage of the non standard conform packages like std_logic_unsigned.

 

These packages are vendor specific packages and were never approved by IEEE!

 

So why does Xilinx promote code snippets that are not in line with the coding rules of IEEE Std. 1076-2008?

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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

Hey @paebbels,

 

So why does Xilinx promote code snippets that are not in line with the coding rules of IEEE Std. 1076-2008?

I could probably simply answer that with: because they don't care about the standard, but the truth is probably a lot more complicated than that.

 

First, the Xilinx tools are way behind regarding IEEE 1076-2008, there are bugs and kinks on all ends and most of the newer constructs do not even work in most of them.

 

Secondly, documentation takes a lot of time and effort, especially if it includes examples which are supposed to work. Simply throwing out 'old' examples because there is a 'new' standard is not something you can do there easily.

 

And finally, they are not really 'promoting' those packages, they are just not pointing out the fact that those are not up-to-date.

 

Personally I can understand your frustration because I face it every time when I try to simulate a piece of VHDL 2008 code which was already tailored to pass the synthesis tool, and the simulator complains about something perfectly valid because it simply doesn't follow the standard.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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paebbels
Explorer
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Registered: ‎04-24-2014

Xilinx claimed in another press release that starting with 2016.3, all source files will be considered VHDL-2008 by default. Currently I can't see this behavior. Even Vivado 2017.2 projects are still using old VHDL-93 syntax.

 

Maybe they noticed that both synthesis and simulation are running into severe problems when 2008 is activated. So it's still disabled by default...

 

Synthesis will produce false netlists when the new ?** operators are used and simulation has race conditions like old iSim. Normally, these should be fixed when using protected types for shared variables, but I can produce the same race conditions with protected types in xSim and VHDL-2008 enabled.

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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

Well, those are not the only problems with VHDL 2008 support, the list goes on and on ...

Especially simulation is more '93 than 2008 ...

 

Let's hope this changes before the next standard is released :)

 

Best,

Herbert

-------------- Yes, I do this for fun!
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paebbels
Explorer
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Registered: ‎04-24-2014

Let's hope this changes before the next standard is released :)

 

I don't think so ....

We'll release VHDL-2017 at the end of the year or in early 2018. Aldec and Synopsis have ensured to support VHDL-2017 by the end of the year or in the 1st half of the next year.

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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

 

We'll release VHDL-2017 at the end of the year or in early 2018.

Ouch ... what's new in VHDL-2017? Anything exciting?

 

Aldec and Synopsis have ensured to support VHDL-2017 by the end of the year or in the 1st half of the next year.

Good to know ... maybe this helps to convince Xilinx to get at least VHDL-2008 finished, but maybe not.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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paebbels
Explorer
Explorer
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Registered: ‎04-24-2014

Here is the list of approved Language Changes.

 

Interesting things for synthesis:

- incomplete types

- view modes (interfaces)

- 64-bit integers and physical types

- new attributes

- a new "assignment" operator

- ...

 

Interesting things for simulation:

- more powerful protected types

- new APIs

- ...

hpoetzl
Voyager
Voyager
3,342 Views
Registered: ‎06-24-2013

Thanks, appreciated!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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