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Participant alexisgrytalms
Participant
149 Views
Registered: ‎04-07-2019

Why does vivado 2019.1 randomly add an useless LUT between clock and FF?

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I don't understand why Vivado 2019.1 adds an LUT for BRAM_0.clk and BRAM_1.clk. BRAM_2.clk is correctly synthesized. That leads to timing failure for the address buses to the BRAMs.

  • The code for all three BRAMs is replicated three times.
  • The blue line is clk200 coming from an MMCM. (using internal BUFGCE)
  • We can see BRAM_2.clk is correctly synthesized as clk200 since it's directly connected to the FF.
  • There is a debug mark but no debug nor ILA.

image.png

image.png

(* mark_debug="true" *) struct packed {
  logic  [12:0]  addr; // 2^13=8KB per block ram
  logic          clk;
  logic  [63:0]  din;
  logic  [63:0]  dout;
  logic          en;
  logic          rst;
  logic  [7:0]   we;
} BRAM_0, BRAM_1, BRAM_2;

assign BRAM_0.clk   = clk200;
assign BRAM_0.din   = '0;
assign BRAM_0.en    = 1'b1;
assign BRAM_0.rst   = sys_reset;
assign BRAM_0.we    = '0;
// Same for BRAM_1 and BRAM_2 always @(posedge BRAM_0.clk) begin if (sys_reset) begin BRAM_0.addr <= '0; end else begin BRAM_0.addr <= BRAM_0.addr + 1'b1; end end
//Same for BRAM_1 and BRAM_2

Expected result:

BRAM_*.clk being synthesized as clk200 without LUT in between that creates a gated clock. Same as BRAM_2.

Thank you.

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1 Solution

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Xilinx Employee
Xilinx Employee
122 Views
Registered: ‎05-14-2008

Re: Why does vivado 2019.1 randomly add an useless LUT between clock and FF?

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Remove the mark_debug from the struct.

Put the mark_debug on the specific signals/nets.

When you put mark_debug on a subject, it adds a "keep" attribute automatically.

In your example, the BRAM_0.clk, BRAM_1.clk, BRAM_2.clk are actually coming from the same clock source but have different names.

The attribute tries to keep each name as it is applied to the struct.

However, one net can only have one name.

So the tool adds two LUTs so that it creates two "new" nets with BRAM_0.clk and BRAM_1.clk name.

-vivian

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3 Replies
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Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎05-14-2008

Re: Why does vivado 2019.1 randomly add an useless LUT between clock and FF?

Jump to solution

Remove the mark_debug from the struct.

Put the mark_debug on the specific signals/nets.

When you put mark_debug on a subject, it adds a "keep" attribute automatically.

In your example, the BRAM_0.clk, BRAM_1.clk, BRAM_2.clk are actually coming from the same clock source but have different names.

The attribute tries to keep each name as it is applied to the struct.

However, one net can only have one name.

So the tool adds two LUTs so that it creates two "new" nets with BRAM_0.clk and BRAM_1.clk name.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Participant alexisgrytalms
Participant
111 Views
Registered: ‎04-07-2019

Re: Why does vivado 2019.1 randomly add an useless LUT between clock and FF?

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Thank you vivian, that's good to know and from now I'll need to be very careful when I use mark_debug.

Lots of useless warnings but no warning for such an important change in the design.

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Participant alexisgrytalms
Participant
97 Views
Registered: ‎04-07-2019

Re: Why does vivado 2019.1 randomly add an useless LUT between clock and FF?

Jump to solution

It seems the mark_debug is ignored when set for a signal in a SystemVerilog struct.

struct packed {
  logic          clk;
  logic          rst;
(* mark_debug="true" *) logic  [12:0]  addr; // 2^13=8KB per block ram
(* mark_debug="true" *) logic  [63:0]  din;
(* mark_debug="true" *) logic  [63:0]  dout;
                        logic          en;
(* mark_debug="true" *) logic  [7:0]   we;
} BRAM_0, BRAM_1, BRAM_2;

 

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