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Newbie chris_choy
Newbie
6,663 Views
Registered: ‎06-09-2016

Why is there a output port unconnected?

I want to design a octal counter from 2 to 9 with a counter module from 0 to 15.

And once it turned to 2 form 9, Q8=0;

I have assigned the 0 to Q8 in the code, but the port Q8 is stilled unconnected.

Can you tell me where is the fault in my code?

Thank you very much! 

 

module octal_counter(
    input CP,M,
    output QA,QB,QC,QD,Q8
    );
    begin
    reg A,B,C,D,LDbar,CLRbar,Q8;
    initial
        begin
            A<=0;
            B<=1;
            C<=0;
            D<=0;
            CLRbar<=1; 
            LDbar<=1;
        end
    //LDbar=0,QD=D,QC=C,QB=B,QA=A
    binary_counter_4bit t1(A,B,C,D,M,LDbar,CLRbar,CP,QA,QB,QC,QD,QCCbar);
    
    always @(posedge CP)
        begin
            if(QD&&QA) //QDQCQBQA=1001,QD=D,QC=C,QB=B,QA=A
                begin
                    Q8=0;
                    LDbar=0;
                end
            else
                begin
                    Q8=1;
                    LDbar=1;
                end
        end
    end
endmodule

1.jpg

 

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4 Replies
Instructor
Instructor
6,630 Views
Registered: ‎08-14-2007

Re: Why is there a output port unconnected?

The only thing I see is that Q8 and LDbar are the same, so it's likely that synthesis has removed the duplicate register.  Does the design work properly in simulation?  If so it's likely that this is just a bug in the schematic creator due to the duplicate register removal.

-- Gabor
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Newbie chris_choy
Newbie
6,609 Views
Registered: ‎06-09-2016

Re: Why is there a output port unconnected?

Thanks for replying.

But I'm afraid that's not the reason. I have tried change to assign the contrary value between Q8 and LDbar under the same condition. But the problem was still exited.

As for the simulation, Q8 was still output value "z" when other input and output are regular.

 

--Chris 

 

2.jpg

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Instructor
Instructor
6,601 Views
Registered: ‎08-14-2007

Re: Why is there a output port unconnected?

What tools are you using?  Vivado?  ISE?

I noticed that your design doesn't do what you wanted, i.e. your load pulse comes a cycle too late to generate a transition from 9 to 2, instead the counter actually counts up to 10 because there is an extra clock delay from detecting state 9 until driving LDbar low.  That still doesn't explain why Q8 is unconnected, though.

Another thing that looks strange is the use of non-blocking assignments in the initial block and blocking assignments in the always block.  Usually it is the other way around like:

 

initial begin

  A = 0;

  B = 1;

  ...

end

 

always @ (posedge CP)

  begin

    if (...)

      Q8 <= 0;

  ...

  end

 

Again, that still doesn't explain the disconnect.

 

-- Gabor
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Newbie chris_choy
Newbie
6,589 Views
Registered: ‎06-09-2016

Re: Why is there a output port unconnected?

Yes you're right. There are some problems in my design. I will make some changes to my design.

And, I'm using Vivado to make it.

How can I fix the "Unconnected" problem?

Thanks.

 

--Chris

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