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Adventurer
Adventurer
11,193 Views
Registered: ‎02-12-2016

XCF error on synthesis: Signal name X not found in design

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Scenario: Ubuntu 64bit, Project Navigator 14.7
I am trying the best I can to avoid trimming by adding constraints (attributes). The design I have started constructing will in some way or another not connect all signals directly to the output, but the numbers are shuffled around and so every signal is eventually necessary. I also want to have a consistent consumption of slices for comparison of various solutions. 

 

First I added attribute S to the vhd file underneath the signal declaration with no effect. Then I added the same attribute to the .ucf file with no effect either. Then I understood after some time looking that the synthesis constraints file (XCF) is the one to deal with if you might be having issues with trimming during synthesis.

 

Now I have the following in the .vhd file:

attribute keep : string;
attribute S      : string;

signal state_in_s   : k_lane;
signal state_out_s  : k_state;

attribute S of state_out_s : signal is "TRUE";
attribute keep of state_out_s : signal is "TRUE";

This in the .ucf file:

#Created by Constraints Editor (xc5vlx50t-ff1136-3) - 2016/02/12
NET "clk_i" TNM_NET = clk_i;
TIMESPEC TS_clk_i = PERIOD "clk_i" 2 ns HIGH 50%;

NET counter keep;
NET "state_out_s" keep;
NET counter S;
NET "state_out_s" S;

and this in the .xcf file:

#Created by Constraints Editor (xc5vlx50t-ff1136-3) - 2016/02/12
NET "clk_i" TNM_NET = clk_i;
TIMESPEC TS_clk_i = PERIOD "clk_i" 2 ns HIGH 50%;

NET counter[0] keep;
NET state_out_s keep;
NET counter[0] S;
NET state_out_s S;

and the synthesis error is:

ERROR:Xst:1370 - Line 6: Signal name counter[0] not found in design.
ERROR:Xst:1370 - Line 7: Signal name state_out_s not found in design.
ERROR:Xst:1370 - Line 8: Signal name counter[0] not found in design.
ERROR:Xst:1370 - Line 9: Signal name state_out_s not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed

I have tried many combinations of numbering behind the signal name etc, hence the inconsistencies. 

 

Sorry for the lack of code, but the attempt to add an attachment failed because the vhdl content did not match the .vhd file extension. 

 

Thanks!

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Moderator
Moderator
19,762 Views
Registered: ‎07-01-2015

Hi @toxup_1,

 

Please go through following link for more information on "keep" attribute.

http://www.xilinx.com/support/answers/54778.html

 

You can use PlanAhead to see the synthesized design.

 

You can also search the nets after post-implementation in PlanAhead.(ctrl+F)

Also you can use save attribute in UCF. For e.g.;NET "state_out_s<0><0>[0]" S= True;

 

Please let me know if your query is addressed.

 

Thanks,
Arpan

Thanks,
Arpan
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11 Replies
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Scholar
Scholar
11,152 Views
Registered: ‎06-05-2013

@toxup_1 Usage seems incorrect for XCF. Please check page no 136 for correct usage

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

-Pratham

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Moderator
Moderator
11,145 Views
Registered: ‎07-01-2015

Hi @toxup_1,

 

Please go through following link:

http://www.xilinx.com/support/answers/18674.html

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
11,131 Views
Registered: ‎02-12-2016

Thanks. However no it doesn't have any effect. The signals are being trimmed away.

 

WARNING:Xst:646 - Signal <state_out_s<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<1><3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <counter> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Adventurer
Adventurer
11,130 Views
Registered: ‎02-12-2016
I've looked at that post and it only tells me to add a Keep attribute which as you can see is present in both my ucf and xcf file.
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Moderator
Moderator
11,121 Views
Registered: ‎07-01-2015

Hi @toxup_1,

 

Please attach the .vhd file.

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
11,116 Views
Registered: ‎02-12-2016

I cannot attach them because of the following errors:

The attachment's stepmapping3.vhd content type (text/x-vhdl) does not match its file extension and has been removed.
The attachment's keccak_globals.vhd content type (text/x-vhdl) does not match its file extension and has been removed.

So please allow me to text dump them here. 

stepmapping3.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

library work;
  use work.keccak_globals.all;


entity Stepmapping is
    Port ( clk_i  : in std_logic;
	         data_i : in std_logic_vector(63 downto 0);
			     data_o : out std_logic_vector(63 downto 0)
			 );
end Stepmapping;

architecture Behavioral of Stepmapping is

-- SIGNALS

attribute keep : string;
attribute S      : string;

signal state_in_s   : k_lane;
signal state_out_s  : k_state;

attribute S of state_out_s : signal is "TRUE";
attribute keep of state_out_s : signal is "TRUE";

signal state_s  : k_state;

type fsm is (latch, scramble);
signal state : fsm :=latch;
signal counter : integer range 0 to 2:=0;


begin

process(clk_i)
begin
  if rising_edge(clk_i) then


    case state is
      when latch =>
        state_s(3)(1) <= state_in_s;
        state_s(2)(2) <= state_s(0)(0);
        state_s(0)(0) <= state_s(2)(2);
        state_out_s <= state_s;
        state <= scramble;

      when scramble =>
        for y in 0 to 4 loop
          for x in 0 to 4 loop
            state_s((((2*x)+(3*y))+2) mod 5)(y mod 5) <= state_s(y)(x);
          end loop;
        end loop;
        state <= latch;
    end case;

  end if;
end process;

i0050: for z in 0 to 63 generate
  state_in_s(z) <= data_i(z);
  data_o(z) <= state_out_s(1)(4)(z);
end generate;

end Behavioral;

Package Keccak_globals:

library IEEE;
  use IEEE.std_logic_misc.all;
  use IEEE.std_logic_1164.all;
    
library work;


package keccak_globals is


constant logD : integer :=4;

constant r : integer:= 1024;      -- bit-rate and size of outer state
constant l : integer:= 256;       -- digest size (conventionally = C/2 = 256 by default)
constant pipeline_nr : integer:=8; -- number of pipelines affect round_counter_s


--types
 type k_lane  is array(63 downto 0) of std_logic;    
 type k_plane is array(4 downto 0)  of k_lane;    
 type k_state is array(4 downto 0)  of k_plane;  
  

end package;

 

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Moderator
Moderator
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Registered: ‎07-01-2015

Hi @toxup_1,

 

I went through your code. Trimming is expected. As output "data_o" is only dependent on state_out_s(1)(4)(63:0)

data_o(z) <= state_out_s(1)(4)(z);

 

Counter is only initialized but never used. So it will be optimized.

WARNING:Xst:646 - Signal <state_out_s<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<1><3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <state_out_s<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <counter> is never used or assigned. This unconnected signal will be trimmed during the optimization process.

 

To preserve the signals please use the following constraints in XCF

BEGIN MODEL "Stepmapping"
NET "state_out_s<4>" keep = yes;
NET "state_out_s<3>" keep = yes;
NET "state_out_s<2>" keep = yes;
NET "state_out_s<1>" keep = yes;
NET "state_out_s<0>" keep = yes;
END;

 

Please let me know if it works.

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
11,093 Views
Registered: ‎02-12-2016
WARNING:Xst:1580 - Signal <state_out_s<4>> with a "KEEP" property is assigned but never used. Related logic will not be removed.

There is progress at least. I also expect the signal to be trimmed away, but it is explained in the constraints documentation that the trimming procedure can be disabled for NETs and signals so I expect that functionality to be available. 

 

Thanks for swift replies btw.

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Adventurer
Adventurer
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Registered: ‎02-12-2016
it is also stated that there is a common misconception regarding the keep constraint's ability to avoid trimming as it only works for output signals or something.
the S constraint should be used instead:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf (p194)
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Moderator
Moderator
19,763 Views
Registered: ‎07-01-2015

Hi @toxup_1,

 

Please go through following link for more information on "keep" attribute.

http://www.xilinx.com/support/answers/54778.html

 

You can use PlanAhead to see the synthesized design.

 

You can also search the nets after post-implementation in PlanAhead.(ctrl+F)

Also you can use save attribute in UCF. For e.g.;NET "state_out_s<0><0>[0]" S= True;

 

Please let me know if your query is addressed.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Adventurer
9,310 Views
Registered: ‎02-12-2016

Thanks!

 

I can see the attributes for the wanted signals (signals that should NOT be trimmed) in the pre-synthesis planahead and they are as I want. I can still see the signals in the post-synthesis planahead.

 

Actually now it works! " Signals will not be removed". Thank you! I will set the attributes in planahead from now on. 

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