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subagha
Visitor
Visitor
3,455 Views
Registered: ‎11-19-2007

XST 11.2 Takes a lot of memory and never completes the synthesis

Hi,

 I tried to synthesize a small example using xst 11.2 but the synthesis takes more than 20 GB of memory and never completes,

So I have to kill the tool.

 

Please find the code Below

 

library ieee;
    use ieee.std_logic_1164.all;

entity tmp is
    port (
        i1 : in     std_ulogic;
        o1 : out    std_ulogic_vector(31 downto 0)
    );
end tmp;



architecture rtl of tmp is
  signal sig1            : std_ulogic_vector(31 downto  0);
  signal sig2    : std_ulogic_vector(15 downto  0);

begin

     tmp_process: process (sig2, sig1)
 
       variable var1 : std_ulogic_vector(15 downto 0);
       variable var2   : std_ulogic_vector(1 downto 0);
       variable var3     : std_ulogic_vector(3 downto 0);
 
     begin
          var3        := (others => '0');
          for i in 15 downto 0 loop
              var2      := sig1((i*2+1) downto (i*2));
              case var2 is
                  when "00" =>
                      var3(0)  := var3(0) or var1(i);
                  when "01" =>
                      var3(1)  := var3(1) or var1(i);
                  when "10" =>
                      var3(2)  := var3(2) or var1(i);
                  when "11" =>
                      var3(3)  := var3(3) or var1(i);
                  when others =>
                      null;
              end case;
         end loop;
     end process;
   
end rtl ;

 

Your help is most appreciated.

 

regards,

subagha

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2 Replies
bassman59
Historian
Historian
3,444 Views
Registered: ‎02-25-2008

You are trying to synthesize a huge combinatorial loop.

 

Don't do that.

----------------------------Yes, I do this for a living.
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eilert
Teacher
Teacher
3,425 Views
Registered: ‎08-14-2007

The same thread can be found on comp.arch.fpga

 

There are already several responses to it.

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