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Visitor
Visitor
4,013 Views
Registered: ‎10-27-2013

XST 646 and XST 1780

Hi guys,

I am student and i am a newbie to xilinx and VHDL.

 

I am using Spartan 3, device XC3S200, version ISE 13.2 for my simulation

 

 

I am trying to write a VHDL code for my project, to perform the state machine as following:  

 

 

Untitled1.png

I write the code as following:

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

 

entity SQRT is

port(A: in std_logic_vector(7 downto 0);

B: in std_logic_vector(7 downto 0);

start: in std_logic;

clk,reset:in std_logic;

done:out std_logic;

Y:out std_logic_vector(16 downto 0));

end entity SQRT;

 

architecture rtl of SQRT is

constant width: integer:=8;

type state_type is (S0,S1,S2,S3,S4);

 

signal state_reg,state_next:state_type;

signal r1_reg, r2_reg: signed (width downto 0);

signal r1_next, r2_next: signed (width downto 0);

signal r3_reg, r4_reg: signed (16 downto 0);

signal r3_next, r4_next:signed (16 downto 0);

signal add1_op0,add1_op1:signed(16 downto 0);

signal add2_op0,add2_op1:signed(16 downto 0);

signal sub_op0,sub_op1:signed (16 downto 0);

signal srl1_op0, srl2_op0:signed (width downto 0);

signal srl1_op1, srl2_op1:integer;

signal max_op0, max_op1:signed (16 downto 0);

signal sum1:signed (16 downto 0);

signal sub:signed (16 downto 0);

signal srl1:signed (width downto 0);

signal srl2:signed (width downto 0);

signal maximum:signed (16 downto 0);

 

function max (     left, right : signed)   return signed is  

begin  -- function max  

if LEFT > RIGHT then return LEFT;    

else return RIGHT;    

end if;  

end function max;  

 

begin --state and adta registers update

 

P1:process(clk,reset)

begin

if reset='0' then state_reg<=S0;

r1_reg<=(others=>'0');

r2_reg<=(others=>'0');

r3_reg<=(others=>'0');

r4_reg<=(others=>'0');

elsif (clk'event and clk='1') then state_reg<=state_next;

r1_reg<=r1_next;

r2_reg<=r2_next;

r3_reg<=r3_next;

r4_reg<=r4_next;

end if;

end process P1;

 

P2:process (start,state_reg,r1_reg, r2_reg, r3_reg, r4_reg,A,B, sum1, sub, srl1, srl2, maximum )

begin

r1_next<=r1_reg;

r2_next<=r2_reg;

r3_next<=r3_reg;

r4_next<=r4_reg;

done<='0';

case state_reg is

 

when S0=>

if start='1' then

r1_next<=signed (A(width-1)&A);

r2_next<=signed (B(width-1)&B);

state_next<=S1; done<='1';

else state_next<=S0; end if;

when S1=> r1_next<=srl1;

r2_next<=srl2;

r3_next<=r1_reg & "00000000";

r4_next<=r2_reg & "00000000";

state_next<=S2;

 

when S2=>

r4_next<=sub;

r3_next<=sum1;

state_next<=S3;

 

when S3=>

r3_next<=maximum;

r4_next<=r2_reg &"00000000";

state_next<=S4;

 

when S4=>

r3_next<=maximum;

state_next<=S0;

end case;

end process P2;

 

CSA1:srl1<=srl1_op0 srl srl1_op1; CSA2:srl2<= srl2_op0 srl srl2_op1;

 

begin

 

case state_reg is

when S0=> srl1_op0<= r1_reg;--C srl1_op1<= 1 ;--D

when others=> srl2_op0<= r2_reg;--A srl2_op1<= 3;--C --operation 2

end case;

end process P3;

 

CSA3:sum1<=add1_op0+add1_op1;

P4: process ( state_reg, r1_reg, r2_reg, r3_reg, r4_reg)

begin

add1_op0<=r4_reg;

add1_op1<=r3_reg;

end process P4;

 

CSA4:sub<=sub_op0 -sub_op1;

 

P5: process ( state_reg, r1_reg, r2_reg, r3_reg, r4_reg)

begin

sub_op0<="00000000"& r2_reg;

sub_op1<=r4_reg;

end process P5;

 

CSA5:maximum<= max(max_op0, max_op1);

 

P6: process ( state_reg, r1_reg, r2_reg, r3_reg, r4_reg)

begin case state_reg is

when S3 =>

max_op0<=r4_reg;

max_op1<=r3_reg;

when others =>

max_op0<=r4_reg;

max_op1<=r3_reg;

end case;

end process P6;

 

output Y<=std_logic_vector(r3_reg);

 

end rtl;

 

 

When I simulate in ISE XST, I got the following warnings:

Xst:646 - Signal <srl2_op0<8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

 

WARNING:Xst:646 - Signal <srl2_op0<8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <srl1_op0<8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <add2_op1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <add2_op0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 9-bit latch for signal <srl2_op0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 9-bit latch for signal <srl1_op0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <srl1_op0_8> of sequential type is unconnected in block <SQRT>.
WARNING:Xst:2677 - Node <srl2_op0_8> of sequential type is unconnected in block <SQRT>.

 

When I put the testbench in to test in ISim, the simulation does not work and the input does not come in

 

I don't know what's wrong, is it problems with the code or simulation? Please guide me

 

Thanks in advance!

 

Untitled1.png

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3 Replies
Highlighted
Scholar
Scholar
3,993 Views
Registered: ‎06-05-2013

Re: XST 646 and XST 1780

Hello,

These are just a warnings.what error are you getting when trying to do simulation.

Regards,
Pratham
-Pratham

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Highlighted
Historian
Historian
3,982 Views
Registered: ‎02-25-2008

Re: XST 646 and XST 1780

The "assigned but never used" warnings are thrown when you do what it says. Why look into why you're not using some bits you're assigning.

 

The "Found 9-bit latch for signal ..." warning is thrown when you have a combinatorial process and you do not assign to a signal for every possible case. And that is EXACTLY what tends to happen when you use the bad coding style known as "two process state machines."

 

Rewrite the code so it uses one synchronous process for the state machine.

 

PS: you seem to have made a cut-and-paste error in the code you posted.

----------------------------Yes, I do this for a living.
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Teacher
Teacher
3,966 Views
Registered: ‎08-14-2007

Re: XST 646 and XST 1780

Hi,

what your diagram shows is not a state machine (FSM) but a pipelined datapath.

FSMs are needed to controll datapaths, especially when conditional operations or feedback loops are involved.

 

All your code about the states is just reducing the performance of this simple and linear datapath.

 

And even if you need to do some synchronisation with external circuitry, the controlling FSM would be much simpler, since it only needs to be triggered ("start" in your code), then count to 3 or 4 and create some DataValid flag ("done" in your code) for the output stage.

(Now guess why "start" and "done"  do not appear in your diagram.)

 

The state diagram for that looks quite different.

Hint: Since most FSMs should run continuously they form closed loops. Your diagram lacks this.

 

Have a nice synthesis

  Eilert

 

 

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