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Visitor sidude
Visitor
7,882 Views
Registered: ‎08-10-2015

XST Post-synthesis simulation differences between Virtex4 and Virtex6

Hi

 

I've been looking at  a problem we've been having in one of our components where a register interface that we have implemented doesn't seem to be behaving correctly. We've used ISE 14.1 and 14.6, and simulated in ISim and ModelSim 6.6d, which both display the weird behavior. I've attached the project, source, simulation and post-synthesis code which display the issue.

 

We write a value (0x3FFF) to a register (in the case of the simulation 0xC) When that register is read back, we would expect 0x3FFF on reg_response_rdata. Indeed with pre-synthesis simulation, and post-synthesis on Virtex4, this is what we find. However on Virtex6 the response is 0x8000. Through trial and error we can fix this by changing line 98 of the source to the commented out line 99. Note that the implementation of pad_reg and pad_vector are identical, save for pad_vector taking the length as an argument.

 

To recreate run ab_dc.do in your favourite simulator. This simulates a register write to pre and post synthesis models. Notice the reads return different results depending on which hardware has been synthesised, and depending on whether pad_reg or pad_vector are used. Note also that the change to fix the behavior on line 98/99 isn't the same register that we try to write to/read from.

 

When it is broken (ie using pad_reg) we get the following warning: WARNING:Xst:2999 - Signal 'debug_counter', unconnected in block 'ab_dc_pre_comp', is tied to its initial value. I'm not sure what the initial value of debug counter can/should be. This warning doesn't appear when using pad_vector.

 

Files in zip:

 

  • ./ab_dc.vhd                                                                                The source
  • ./WarningOutput.txt                                                                   A comparision of the warnings from ISE14.1 when compiling for Virtex6. Broken = pad_reg, Fixed = pad_vector
  • ./xilinxTest.ise                                                                           The ISE project file
  • ./netgen/synthesis/v4_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex4 using ISE14.1 using pad_reg
  • ./netgen/synthesis/v6_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_reg
  • ./netgen/synthesis/v6_fix_ab_dc_comp_synthesis.vhd            ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_vector
  • ./sim/ab_dc.do                                                                           TCL to compile and run simulation
  • ./sim/ab_dc_tb.vhd                                                                    Simulation to write to register 0xC and then read from it.
  • ./sim/wave.do                                                                            Useful signals to recreate problem

This looks to me like a bug in XST. I'm happy to be proven wrong though!

 

Thanks

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1 Reply
Moderator
Moderator
7,706 Views
Registered: ‎07-21-2014

Re: XST Post-synthesis simulation differences between Virtex4 and Virtex6

@sidude

 

Looks like a parser issue to me, in case of V4 device XST uses an old parser and for V6 devices XST uses new parser. Check below AR:

http://www.xilinx.com/support/answers/32927.html

 

Thanks,
Anusheel
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