cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
5,899 Views
Registered: ‎07-24-2011

XST Synthesis Error

Jump to solution

Hi,

 

I'm getting a strange error during synthesis using XST:

 

ERROR:Xst:2862 - Unit <project_main> : The conversion of memory element <Abo_1> to macro RAM failed, because a memory port is unknown. Please review the Xilinx resources documentation and the XST user manual for coding guidelines or check the warning messages in the log file about this memory element.

 

I do have a variable named Abo, but the log file has no warning messages about this memory element, it only has unrelated warnings. I searched for someone having a similar problem and absolutely nothing came up. Does anyone know what this problem pertains to?

 

Thanks

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
7,439 Views
Registered: ‎07-24-2011

Aaaaaaaaaaand for some strange reason, after making other seemingly unrelated changes to my code, this problem has gone away. Strange stuff...

View solution in original post

0 Kudos
6 Replies
Highlighted
Scholar
Scholar
5,898 Views
Registered: ‎02-27-2008
s,

What is the variable Abo: a single bit, a 32 bit word, a matrix?

The synthesis tool is complaining that it can't map the variable to a memory that it knows about (in the FPGA). Something about this variable is problematic.
Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Visitor
Visitor
5,894 Views
Registered: ‎07-24-2011

Sorry, I should have mentioned that. The variable is defined as follows:

 

type Abo_x is array(1 downto 0, 3 downto 0) of std_logic_vector(31 downto 0);

signal Abo : Abo_x := ((others => (others => X"00000000")));

 

I have many other variables in my project that are defined and used in the same way, but it does not complain about those (yet).

0 Kudos
Highlighted
Visitor
Visitor
5,890 Views
Registered: ‎07-24-2011

I think I found what the problem is. I'm using the variable for this function:

 

for i1 in 0 to 1 loop

     for j1 in 0 to 3 loop

          if (Aboresult(i1,j1) = B"1") then

                    Abo(i1,j1) <= X"3F800000";

          else

                    Abo(i1,j1) <= X"00000000";

          end if;

     end loop;

end loop;

 

When I comment out the second half of the if-statement (e.g, the lines containing else and Abo(i1,j1) <= X"00000000"), the problem goes away. What is going on? Why doesn't it like this?

0 Kudos
Highlighted
Visitor
Visitor
7,440 Views
Registered: ‎07-24-2011

Aaaaaaaaaaand for some strange reason, after making other seemingly unrelated changes to my code, this problem has gone away. Strange stuff...

View solution in original post

0 Kudos
Highlighted
Professor
Professor
5,866 Views
Registered: ‎08-14-2007

@scanframer wrote:

Aaaaaaaaaaand for some strange reason, after making other seemingly unrelated changes to my code, this problem has gone away. Strange stuff...


ISE has a habit of holding on to old bits of pre-compiled stuff unless you "clean-up project files."  Perhaps

you were being bitten by that bug.  Just as an aside, though...  The "memory" you described could not

actually be implemented as RAM because (especially with the "else" clause in your loop) it could have

all of its elements written in a single clock cycle.  That should not prevent synthesis from creating the

matrix from slice flip-flops, however.  It's possible that some lingering bits of pre-compiled stuff had already

made a decision to use RAM for the structure, causing the error.

 

Regards,

Gabor

-- Gabor
0 Kudos
Highlighted
Newbie
Newbie
5,798 Views
Registered: ‎08-30-2012

Hi I think I have a similar problem.  During synthesis I receive the following error message:

 

EXCEPTION:Xdm:Signal.c:191:$Id: Signal.c,v 1.19 2009/06/12 19:55:29 jdl Exp $ - Xdm_Exception::IllegalPinSignal signal '/outputBuffer/SOURCE/outputBuffer/_n14978<32>' is not a peer or child of pin '/XSTMACRO_RAM_50/SOURCE/XSTMACRO_RAM_50/diA<15>'

 

I've narrowed it down to the following lines in my code causing this error:

 

 

                STATE 1:

 for (j=0; j < 10; j=j+1)

                                   begin

                                      idx1 = Table1[Counter][j];

                                      idx2 = Table2[idx1];                                     

                                      Data[j] = !(Arr1[idx1] && Arr2[idx2]);

                                   end

 

 

                STATE 2:

 for (j=0; j < 10; j=j+1)

                                   begin

                                      idx1 = Table1[Counter][j];

                                      idx2 = Table2[idx1];                                     

                                      Data[j] = (Arr1[idx1] && Arr2[idx2]);

                                   end

 

If i comment out the line in bold, the error goes away.   Any ideas why this is happening?

 

Thanks,

DL

0 Kudos