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Registered: ‎02-17-2018

Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_4> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.

 

My final project is fpga based bluetooth control to dual dc motor car. I can receive the data from my bluetooth modle. But i can not process the received data on my fpga hardware. I reasearched the problem on xilinx supports and different websites. I arranged the code as they are said. But this problem is still going.  Here is my last version of code :

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity robocar_control is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
r_pos : out STD_LOGIC;
r_neg : out STD_LOGIC;
l_pos : out STD_LOGIC;
l_neg : out STD_LOGIC);

end robocar_control;

 

architecture Behavioral of robocar_control is

 

component top_mod1
generic
(PWM_WIDTH : integer := 16;
PWM_PERIOD : integer := 50000);
port
(clk, reset : in std_logic;
desiredDuty : in std_logic_vector(6 downto 0);
pwm_out : out std_logic);
end component;

 

component top_mod2
generic

(PWM_WIDTH : integer := 16;
PWM_PERIOD : integer := 50000);
port
(clk, reset : in std_logic;
desiredDuty : in std_logic_vector(6 downto 0);
pwm_out : out std_logic);
end component;

 

component top_mod3
generic
(PWM_WIDTH : integer := 16;
PWM_PERIOD : integer := 50000);
port
(clk, reset : in std_logic;
desiredDuty : in std_logic_vector(6 downto 0);
pwm_out : out std_logic);
end component;

 

component top_mod4
generic
(PWM_WIDTH : integer := 16;
PWM_PERIOD : integer := 50000);
port
(clk, reset : in std_logic;
desiredDuty : in std_logic_vector(6 downto 0);
pwm_out : out std_logic);
end component;


type state is (ready,start1);
signal ps1 : state := ready;
signal start,stop : std_logic;
signal out_pin1, out_pin2, out_pin3, out_pin4 : std_logic;
signal desiredDuty_r_pos, desiredDuty_r_neg, desiredDuty_l_pos, desiredDuty_l_neg : std_logic_vector(6 downto 0):= "0000000";
signal store :std_logic_vector(7 downto 0) := "00000000";

begin

 

uut1: top_mod1
port map(clk => clk, reset => reset, desiredDuty => desiredDuty_r_pos,
pwm_out => out_pin1);
uut2: top_mod2
port map(clk => clk, reset => reset, desiredDuty => desiredDuty_r_neg,
pwm_out => out_pin2);
uut3: top_mod3
port map(clk => clk, reset => reset, desiredDuty => desiredDuty_l_pos,
pwm_out => out_pin3);
uut4: top_mod4
port map(clk => clk, reset => reset, desiredDuty => desiredDuty_l_neg,
pwm_out => out_pin4);

 

second1 : process(clk)
variable i : integer := 0;
begin
    if clk'event and clk = '1' then

       if ps1 = ready then 
       start <= din;
       end if;
----------------start bit detect logic-----------------
       if start = '0' then
       ps1 <= start1;
       else
       ps1 <= ready;
       end if;

---------------------16xbaudrate sampling mathod---------------------------
        if ps1 = start1 then
        i := i + 1;

          if i = 2600 then
          start <= din;
          end if;

          if i = 7800 then
         store(0) <= din;
         end if;

         if i = 13000 then
         store(1) <= din;
         end if;
 
         if i = 18200 then
         store(2) <= din;
         end if;

 

        if i = 23400 then
        store(3) <= din;
        end if;

 

        if i = 28600 then
        store(4) <= din;
        end if;

 

        if i = 33800 then
        store(5) <= din;
        end if;

        if i = 39000 then
        store(6) <= din;
        end if;

 

        if i = 44200 then
        store(7) <= din;
        end if;

        if i = 49400 then
        stop <= din;
        end if;

 

       if i = 54600 then
       i := 0;
       ps1 <= ready;
       end if;

 

    end if;
 end if;
end process;

 

--dout <= store(7 downto 0);

 

second2 : process(clk,reset,store,out_pin1, out_pin2, out_pin3, out_pin4)


variable i,j : integer := 0;

 

begin


          if reset='1' then
          desiredDuty_r_pos <= "0000000";
          desiredDuty_r_neg <= "0000000";
          desiredDuty_l_pos <= "0000000";
          desiredDuty_l_neg <= "0000000";

           elsif rising_edge(clk) then

           if store = x"46" then --- forward F
           j := 0;
           i := i + 1;
           if i <= 1005000 then

            desiredDuty_r_pos <= "0000000";
            desiredDuty_l_pos <= "0000000";

            elsif i > 1005000 and i < 1550000 then

            desiredDuty_r_pos <= "1100011";
            desiredDuty_l_pos <= "1100011";

            elsif i = 1550000 then
            i := 0;
            end if;

            desiredDuty_r_neg <= "0000000";
            desiredDuty_l_neg <= "0000000";

           elsif store = x"42" then ---backward B
           i := 0;
           j := j + 1;
          if j <= 1005000 then

          desiredDuty_r_neg <= "0000000";
          desiredDuty_l_neg <= "0000000";

          elsif j > 1005000 and j < 1550000 then

          desiredDuty_r_neg <= "1100011";
          desiredDuty_l_neg <= "1100011";

          elsif i = 1550000 then
          j := 0;
         end if;

        desiredDuty_r_pos <= "0000000";
        desiredDuty_l_pos <= "0000000";

       

        else
          null;

      end if;
 end if;

r_pos <= out_pin1;
r_neg <= out_pin2;
l_pos <= out_pin3;
l_neg <= out_pin4;

end process;

end Behavioral;

 

 

Here is my top modules : 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity top_mod1 is
generic
(
PWM_WIDTH : integer := 16;
PWM_PERIOD : integer := 50000
);
port
(
clk, reset : in std_logic;
desiredDuty : in std_logic_vector(6 downto 0);
pwm_out : out std_logic
);
end top_mod1;

 

architecture Behavioral of top_mod1 is
signal pwmCmp :std_logic_vector(15 downto 0);
begin
pwmInst : entity work.pwm_gen1(arch)
generic map(PWM_CNT => PWM_PERIOD, WIDTH => PWM_WIDTH)

port map(clk => clk, reset => reset, pwmCmp => pwmCmp,
pwm_out => pwm_out);

dutyROM: entity work.duty1(rom) port map(addr => desiredDuty, data => pwmCmp,clk => clk, reset => reset );

end Behavioral;

 

 

Here is sub-module of top_module :

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


use IEEE.NUMERIC_STD.ALL;

 

entity duty1 is
port
(
clk, reset : in std_logic;
addr : in std_logic_vector(6 downto 0);
data : out std_logic_vector(15 downto 0)
);
end duty1;

architecture rom of duty1 is
constant ADDR_WIDTH : integer := 7;
constant DATA_WIDTH : integer := 16;
type rom_type is array(0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);

constant duty1 : rom_type := (1 => std_logic_vector(to_unsigned(500,16)),
2 => std_logic_vector(to_unsigned(1000,16)),
3 => std_logic_vector(to_unsigned(1500,16)),
4 => std_logic_vector(to_unsigned(2000,16)),
5 => std_logic_vector(to_unsigned(2500,16)),
6 => std_logic_vector(to_unsigned(3000,16)),
7 => std_logic_vector(to_unsigned(3500,16)),
8 => std_logic_vector(to_unsigned(4000,16)),
9 => std_logic_vector(to_unsigned(4500,16)),
10 => std_logic_vector(to_unsigned(5000,16)),
11 => std_logic_vector(to_unsigned(5500,16)),
12 => std_logic_vector(to_unsigned(6000,16)),
13 => std_logic_vector(to_unsigned(6500,16)),
14 => std_logic_vector(to_unsigned(7000,16)),
15 => std_logic_vector(to_unsigned(7500,16)),
16 => std_logic_vector(to_unsigned(8000,16)),
17 => std_logic_vector(to_unsigned(8500,16)),
18 => std_logic_vector(to_unsigned(9000,16)),
19 => std_logic_vector(to_unsigned(9500,16)),
20 => std_logic_vector(to_unsigned(10000,16)),
21 => std_logic_vector(to_unsigned(10500,16)),
22 => std_logic_vector(to_unsigned(11000,16)),
23 => std_logic_vector(to_unsigned(11500,16)),
24 => std_logic_vector(to_unsigned(12000,16)),
25 => std_logic_vector(to_unsigned(12500,16)),
26 => std_logic_vector(to_unsigned(13000,16)),
27 => std_logic_vector(to_unsigned(13500,16)),
28 => std_logic_vector(to_unsigned(14000,16)),
29 => std_logic_vector(to_unsigned(14500,16)),
30 => std_logic_vector(to_unsigned(15000,16)),
31 => std_logic_vector(to_unsigned(15500,16)),
32 => std_logic_vector(to_unsigned(16000,16)),
33 => std_logic_vector(to_unsigned(16500,16)),
34 => std_logic_vector(to_unsigned(17000,16)),
35 => std_logic_vector(to_unsigned(17500,16)),
36 => std_logic_vector(to_unsigned(18000,16)),
37 => std_logic_vector(to_unsigned(18500,16)),
38 => std_logic_vector(to_unsigned(19000,16)),
39 => std_logic_vector(to_unsigned(19500,16)),
40 => std_logic_vector(to_unsigned(20000,16)),
41 => std_logic_vector(to_unsigned(20500,16)),
42 => std_logic_vector(to_unsigned(21000,16)),
43 => std_logic_vector(to_unsigned(21500,16)),
44 => std_logic_vector(to_unsigned(22000,16)),
45 => std_logic_vector(to_unsigned(22500,16)),
46 => std_logic_vector(to_unsigned(23000,16)),
47 => std_logic_vector(to_unsigned(23500,16)),
48 => std_logic_vector(to_unsigned(24000,16)),
49 => std_logic_vector(to_unsigned(24500,16)),
50 => std_logic_vector(to_unsigned(25000,16)),
51 => std_logic_vector(to_unsigned(25500,16)),
52 => std_logic_vector(to_unsigned(26000,16)),
53 => std_logic_vector(to_unsigned(26500,16)),
54 => std_logic_vector(to_unsigned(27000,16)),
55 => std_logic_vector(to_unsigned(27500,16)),
56 => std_logic_vector(to_unsigned(28000,16)),
57 => std_logic_vector(to_unsigned(28500,16)),
58 => std_logic_vector(to_unsigned(29000,16)),
59 => std_logic_vector(to_unsigned(29500,16)),
60 => std_logic_vector(to_unsigned(30000,16)),
61 => std_logic_vector(to_unsigned(30500,16)),
62 => std_logic_vector(to_unsigned(31000,16)),
63 => std_logic_vector(to_unsigned(31500,16)),
64 => std_logic_vector(to_unsigned(32000,16)),
65 => std_logic_vector(to_unsigned(32500,16)),
66 => std_logic_vector(to_unsigned(33000,16)),
67 => std_logic_vector(to_unsigned(33500,16)),
68 => std_logic_vector(to_unsigned(34000,16)),
69 => std_logic_vector(to_unsigned(34500,16)),
70 => std_logic_vector(to_unsigned(35000,16)),
71 => std_logic_vector(to_unsigned(35500,16)),
72 => std_logic_vector(to_unsigned(36000,16)),
73 => std_logic_vector(to_unsigned(36500,16)),
74 => std_logic_vector(to_unsigned(37000,16)),
75 => std_logic_vector(to_unsigned(37500,16)),
76 => std_logic_vector(to_unsigned(38000,16)),
77 => std_logic_vector(to_unsigned(38500,16)),
78 => std_logic_vector(to_unsigned(39000,16)),
79 => std_logic_vector(to_unsigned(39500,16)),
80 => std_logic_vector(to_unsigned(40000,16)),
81 => std_logic_vector(to_unsigned(40500,16)),
82 => std_logic_vector(to_unsigned(41000,16)),
83 => std_logic_vector(to_unsigned(41500,16)),
84 => std_logic_vector(to_unsigned(42000,16)),
85 => std_logic_vector(to_unsigned(42500,16)),
86 => std_logic_vector(to_unsigned(43000,16)),
87 => std_logic_vector(to_unsigned(43500,16)),
88 => std_logic_vector(to_unsigned(44000,16)),
89 => std_logic_vector(to_unsigned(44500,16)),
90 => std_logic_vector(to_unsigned(45000,16)),
91 => std_logic_vector(to_unsigned(45500,16)),
92 => std_logic_vector(to_unsigned(46000,16)),
93 => std_logic_vector(to_unsigned(46500,16)),
94 => std_logic_vector(to_unsigned(47000,16)),
95 => std_logic_vector(to_unsigned(47500,16)),
96 => std_logic_vector(to_unsigned(48000,16)),
97 => std_logic_vector(to_unsigned(48500,16)),
98 => std_logic_vector(to_unsigned(49000,16)),
99 => std_logic_vector(to_unsigned(50000,16)),
others => std_logic_vector(to_unsigned(0,16)));

begin

process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
data <= (others => '0');
else
data <= duty1( to_integer( unsigned( addr ) ) );

end if;
end if;
end process;


end rom;

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity pwm_gen1 is
generic
(
PWM_CNT : integer := 50000; -- for 1ms period
WIDTH : integer := 16 -- in order to accommdate 1000000 count
);
port
(
clk, reset : in std_logic;
pwmCmp : in std_logic_vector(WIDTH-1 downto 0); -- from duty ROM
pwm_out : out std_logic
);
end pwm_gen1;

architecture arch of pwm_gen1 is
signal pwm_reg, pwm_next : unsigned( WIDTH-1 downto 0 );
begin
process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
pwm_reg <= (others => '0');
else
pwm_reg <= pwm_next;

end if;
end if;
end process;

pwm_next <= (others => '0')
when (pwm_reg = PWM_CNT-1)
else
pwm_reg + 1;
pwm_out <= '1'
when ( pwm_reg < unsigned(pwmCmp) )
else
'0';
end arch;

 

Here is my error warnings : 

 

WARNING:Xst:646 - Signal <stop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <desiredDuty_l_pos_2> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_pos_3> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_pos_4> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_2> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_3> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_4> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <desiredDuty_l_pos_2> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_pos_3> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_pos_4> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_2> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_3> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <desiredDuty_l_neg_4> has a constant value of 0 in block <robocar_control>. This FF/Latch will be trimmed during the optimization process.

 

 

I reasearched many times on xilinx supports and forums. i arranged my code but i didn't progress to it. Also, i run sub module of  the code (top_mod1, top_mod2, top_mod3, top_mod4) i didn't get any error or warnings. So, top_mod1,2,3,4 works nicely. The problem is on the main module. when i look the warnings i thought that the process of clk is wrong. How can I get over it? Give me a path  or   directs me  please...

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