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Contributor
Contributor
6,036 Views
Registered: ‎08-07-2008

Yet Another Synchronous Reset Post

I already use synchronous resets, so it's not that question again. I'm getting up on speed on Vivado. Being able to easily call up a schematic for any block is a neat feature.

 

It might be nothing, but I have spotted several signals where (post synthesis) the synchronous reset is not routed directly to a RST or SET port but gets routed through a LUT and combined with the data signal. Is this normal behavior? Is there something I could be doing in the code that causes this? Or is it no big deal as it is still synchronous and the tool simply decided it was better that way?

 

I don't have any code that would be practical to post because it's many pages. I'm trying to create a easy example, but so far the resets have routed to RST/SET ports just fine. I can't make a simple example where a LUT gets involved.

 

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Guide
Guide
6,024 Views
Registered: ‎01-23-2009

Take a look at this forum thread which discusses control set reduction.

 

Avrum

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Contributor
Contributor
5,965 Views
Registered: ‎08-07-2008

That's the answer I was after. Thanks!

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