09-14-2020 07:50 AM
I am using Vivado 2018.3 and am trying to build a modified version of the MTS example design. All I have done is add 2 AXI GPIOs to the design, and left everything else alone. When I try to generate the bitstream, the process hangs when synthesizing the "zcu111_rfsoc_trd_usp_rf_data_converter_0_0_synth_1". I have left it running for 48 hours straight over a weekend and it never got past this step.
My synthesis settings are set to default:
This is fresh install of Vivado install. Others around me do not have this issue with the same settings and code so I am not to sure what could be wrong. Any design that has this rf_data_converter hangs on synthesis.
09-23-2020 11:17 PM
This looks like an IP OOC synth run. Where did you see that it hang at this step?
If it is a run under the IP OOC synth runs in the Design Runs tab, you can find the synthesis log file in the corresponding run folder under xxxx.runs directory. Check the log file to see if there is any error message.
09-24-2020 08:36 AM
I have looked through the log file for this run and cannot find any errors, only warnings. I attached it to this reply so you can have a look and let me know if there is anything I missed.
I have tried to build this design on 2 different machines, with fairly similar specs, and the full build (synthesis, implementation, and bitstream generation) only takes about 7 hours. Whereas on my machine, I left the build running for over 48 hours and it did not get past this OOC run.
09-26-2020 06:37 PM
"TclStackFree: incorrect freePtr. Call out of sequence?"
This is the last line in the log file.
Usually this message indicates an out of memory issue. So please check if your machine had run out of memory when the error occurred.
09-29-2020 11:40 AM - edited 09-29-2020 11:41 AM
If the same design is wokring on other machines and failing on your machine, then this might be a machine specific issue.
May I know which OS is used? Supported OS with 2018.3: