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embedded
Advisor
Advisor
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Registered: ‎06-09-2011

ZYNQ Ultrascale+ wrong clock setting

Hi all,

I am working on an old design(ZCU104 board) in Vivado2018.1 which I am going to export it to Vivado2020.1 and compile it there. The problem is that I receive below message in Vivado2020. When I want to compile it, I receive strange Error message and do not know where I have to modify the parameter:

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'DP VIDEO(PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ)' with value '320' for BD Cell 'My_Zynq_ultra'. Error: 320.000 MHz is out of range for the parameter: PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ. Valid input frequency range is [0 : 300] MHz

I would appreciate if someone can tell me where i have to modify the PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ parameter to maximum of 300.MHz as noted in the message.

 

Thanks,
Hossein
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