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Registered: ‎05-01-2009

a problem in synthesis report

Hello...

 

I have designed a state machine to control a specific circuit in my design>

My state machine consists of 15 states and many input and output ports to control my circuit

 

BUT, when i synthesis the FSM the following warning appeare in synthsis report :-

 

Synthesizing Unit <controller>.
    Related source file is "D:/my_work/ISE_work/test/controller.vhd".
    Using one-hot encoding for signal <state>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 81 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
    - add an 'INIT' attribute on signal <state> (optimization is then done without any risk)
    - use the attribute 'signal_encoding user' to avoid onehot optimization
    - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization

 

so, what is the meaning of that ??? what is the risk if i ignored this warning ???

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Historian
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6,036 Views
Registered: ‎02-25-2008

Re: a problem in synthesis report


atatt2020 wrote:

Hello...

 

I have designed a state machine to control a specific circuit in my design>

My state machine consists of 15 states and many input and output ports to control my circuit

 

BUT, when i synthesis the FSM the following warning appeare in synthsis report :-

 

Synthesizing Unit <controller>.
    Related source file is "D:/my_work/ISE_work/test/controller.vhd".
    Using one-hot encoding for signal <state>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 81 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
    - add an 'INIT' attribute on signal <state> (optimization is then done without any risk)
    - use the attribute 'signal_encoding user' to avoid onehot optimization
    - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization

 

so, what is the meaning of that ??? what is the risk if i ignored this warning ???


Did you use the usual, and recommended, method of defining states, which is to use an enumerated type?

 

    type state_t is (

        S_RESET,

        S_IDLE,

        S_FOO,

        S_BAR,

        S_BLETCH);

    signal iState : state_t;

 

    Machine : process (clk) is

        ClockEdge : if rising_edge(clk) then

            isReset : if rst = '1' then

                iState <= S_RESET;

                foo <= '0';

                bar <= '0'; 

                bletch <= '0'; 

            else

               Decoder : case iState is

                   when S_RESET : 

                       foo <= '0';

                       bar <= '0'; 

                       bletch <= '0'; 

                       iState <= S_IDLE;

                   when S_IDLE =>

                       if (do_foo) then

                           foo <= '1';

                            bletch <= '0';

                           iState <= S_FOO;

                       end if;

                   when S_FOO =>

                       if (do_bar) then

                           bar <= '1';

                           foo <= '0';

                           iState <= S_BAR;

                       end if;

                   when S_BLETCH =>

                       if (do_bletch) then

                           bletch <= '1';

                           bar <= '0';

                           iState <= S_IDLE;

                       end if;

                   when others =>

                       iState <= S_RESET;

               end case Decoder;

           end if isReset;

        end if ClockEdge;

    end process Machine; 

 

The point here is that you DO NOT give specific definitions for the states. You simply let the synthesis tool determine how many flip-flops are required to store the state register, and it all just works.

 

-a

----------------------------Yes, I do this for a living.
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Highlighted
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Registered: ‎03-17-2009

Re: a problem in synthesis report

in addition to the above response. you could also look at this:

 

In the systhesis options (depending on your ISE version) you will find options like 'case implementation', 'mux extraction', 'FSM encoding style' etc. A more conservative setting (ex: FSM encoding -> none) with these options would result in your warning to go away.

 

The trade-off is a code that might not be a completely optimized code (maybe in terms of speed or area).  most cases that is alright. If you have a problem in terms of fitting or speed, you would have to revisit the code and these options once again.

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Historian
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Registered: ‎02-25-2008

Re: a problem in synthesis report


ekrish01@textron.com wrote:

in addition to the above response. you could also look at this:

 

In the systhesis options (depending on your ISE version) you will find options like 'case implementation', 'mux extraction', 'FSM encoding style' etc. A more conservative setting (ex: FSM encoding -> none) with these options would result in your warning to go away.

 


When using an enumerated type to define the states, changing the synthesis option doesn't cause that error nor make it go away. "Mux extraction" is not important here, and "case implementation" is only for Verilog.

 

The only time I've seen that error is when I've tried to synthesize code that has user-defined states. Say you know your state machine needs ten states, and you define a four-bit state register and four-bit constants for each state (four bits are needed for ten states). Now if you use the synthesis options to change the FSM encoding to one-hot, the synthesis tool will change the state register to be ten bits wide (up from four) and redefine all of your states. And it will helpfully inform you that it did so.

 

Again, the proper way to define states for a state machine is to use the enumerated type. This allows the synthesis tool the most freedom to implement the state machine in the "best" way. And changes in the "FSM Encoding" option will be effective and no warnings/infos will be issued.

 

-a

----------------------------Yes, I do this for a living.
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