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Teacher muzaffer
Teacher
14,554 Views
Registered: ‎03-31-2012

accessing systemverilog interface parameters

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I have an interface definition like this:

 

interface foo #(BAR=50) (input clk, rst); 

...

endinterface

 

Later this interface gets passed to a module and the interface parameter is used in a signal definition.

 

foo f1(.clk(), .rst());

 

module baz(foo f1);

 

logic [f1.BAR:0] b1;

 

When I try to synthesize this I get an error which says "constant expression cannot contain a hierarchical identifier". I have seen some discussion about this on the SV-BC list but I am not sure what they have concluded. Any ideas how to implement something like this ?

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Moderator
Moderator
9,504 Views
Registered: ‎07-21-2014

Re: accessing systemverilog interface parameters

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@muzaffer@jmartel

 

I checked a small test case with 2016.2 and its working at my end. Can you check and confirm?

 

Thanks,
Anusheel
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Xilinx Employee
Xilinx Employee
14,541 Views
Registered: ‎10-24-2013

Re: accessing systemverilog interface parameters

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Hi,
Try doing as mentioned in the below example.

interface Channel #(parameter N = 0)
(input bit Clock, bit Ack, bit Sig);
bit Buff[N-1:0];
initial
for (int i = 0; i < N; i++)
Buff[i] = 0;
always @ (posedge Clock)
if(Ack = 1)
Sig = Buff[N-1];
else
Sig = 0;
endinterface
// Using the interface
module Top;
bit Clock, Ack, Sig;
// Instance the interface. The parameter N is set to 7using named
// connection while the ports are connected using implicit connection
Channel #(.N(7)) TheCh (.*);
TX TheTx (.Ch(TheCh));
...
endmodule
Thanks,Vijay
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Teacher muzaffer
Teacher
14,535 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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unfortunately this doesn't help me. What I am trying to do is to figure out what N is with in the module TX in your example. ie:

 

module TX(channel Ch);

logic [Ch.N:0] foo;

endmodule

 

Vivado thinks this is a hierarchical access but it really is not. The interesting part is that axi.aclk type hierarchical references work (supposing an interface instance named axi with a port called aclk) but axi.WIDTH does not work (where WIDTH is a parameter) with an error saying hierarchical access is not supported. I think it's a bug in Vivado synthesis.

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Xilinx Employee
Xilinx Employee
14,526 Views
Registered: ‎10-24-2013

Re: accessing systemverilog interface parameters

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Can you give me the testcase to check at my end?
Thanks,Vijay
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Teacher muzaffer
Teacher
14,511 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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top.sv:

interface test_if #(WIDTH = 32) (input aclk, aresetn); logic [WIDTH:0] wide; endinterface module top( input reset, input sys_clk); test_if test_if(.aclk(sys_clk), .aresetn(reset)); always @(posedge test_if.aclk) begin:test reg [test_if.WIDTH:0] testvec; testvec <= 0; end endmodule

 Try the above top.sv with the following script & command line "vivado -mode tcl -source test.tcl

 

test.tcl:

create_project -in_memory -part xc7k325tffg900-2
set_property target_language Verilog [current_project]
set_property board xilinx.com:kintex7:kc705:1.1 [current_project]

read_verilog -sv {
  top.sv
}

synth_design -top top -part xc7k325tffg900-2

 

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Xilinx Employee
Xilinx Employee
14,476 Views
Registered: ‎10-24-2013

Re: accessing systemverilog interface parameters

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Hi,
I have filed a CR#770501 for this issue. I will keep you posted on the developments.
Thanks,Vijay
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Visitor akash_0406
Visitor
13,881 Views
Registered: ‎10-07-2013

Re: accessing systemverilog interface parameters

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Is this fixed in 2014.1?

I see the same problem with structures as well.

 

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Visitor chiggs_pv
Visitor
13,350 Views
Registered: ‎08-25-2014

Re: accessing systemverilog interface parameters

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Any update on this?

 

I'm also encountering the same issue.

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Xilinx Employee
Xilinx Employee
13,288 Views
Registered: ‎07-01-2010

Re: accessing systemverilog interface parameters

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Hi,

Accessing systemverilog interface parameters is not supported currently.

Regards,
Achutha
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Teacher muzaffer
Teacher
13,134 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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does this mean this issue won't be fixed for 2014.3 either?
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Scholar markcurry
Scholar
9,266 Views
Registered: ‎09-16-2009

Re: accessing systemverilog interface parameters

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Another way of trying to do this, which should work, but still doesn't (taking your example):

top.sv:

interface test_if #(WIDTH = 32) (input aclk, aresetn);
logic [WIDTH:0] wide;

function integer get_width();
  get_width = WIDTH;
endfunction

endinterface

module top( input        reset,
 input        sys_clk);


test_if test_if(.aclk(sys_clk), .aresetn(reset));

always @(posedge test_if.aclk) begin:test
	reg [test_if.get_width():0] testvec;
	testvec <= 0;
end
endmodule

 

I change what looked like a hier. ref for the tool into a Constant function (albeit a function defined within the interface). Constant functions have been supported for a while, so I thought this might do the trick.

 

This doesn't work with Vivado either, and it should.

 

Vijay - Can you add this variant to the testcase?

 

Thanks,

 

Mark

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Observer glester
Observer
8,900 Views
Registered: ‎03-04-2009

Re: accessing systemverilog interface parameters

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Has anyone found an answer to this?

I'm having the same problem with 2014.4

ERROR: "[Synth 8-660] unable to resolve '<function name>'"

I've tried the interface with and without modports, and with and without the full import function prototype in the modport.  I've tried the function both as a constant and non-constant, as automatic and not.  The error is unassailable.

Thanks,

Gerry

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Teacher muzaffer
Teacher
8,862 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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Another way to do something similar is to use $bits. If you are trying to find the size of an object/type it should (does) work. I am doing this right now:

module foo  #(type IT = complex, type OT=complex) (
input rst,
input clk,
input IT in,
output OT out
);

logic signed [$bits(in.i)-1:0] fooi, fooq;

...

where complex is a struct which has i & q elements of parameterized size.

 

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Visitor jmartel
Visitor
4,540 Views
Registered: ‎07-12-2016

Re: accessing systemverilog interface parameters

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Does anybody have something new on this topic?

I'm currently working with Vivado 2016.1 and still having the same issue...

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Teacher muzaffer
Teacher
4,525 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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@vijayak any update on this issue? What happened with CR#770501 ? 

 

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Moderator
Moderator
9,505 Views
Registered: ‎07-21-2014

Re: accessing systemverilog interface parameters

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@muzaffer@jmartel

 

I checked a small test case with 2016.2 and its working at my end. Can you check and confirm?

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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Visitor jmartel
Visitor
4,479 Views
Registered: ‎07-12-2016

Re: accessing systemverilog interface parameters

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I tested back my use case with 2016.2 and it doesn't seem to work either.

Could you please send me your "small test case" example so I can compare if it matches my code requirements?

 

Thanks,

Joe

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Teacher muzaffer
Teacher
4,462 Views
Registered: ‎03-31-2012

Re: accessing systemverilog interface parameters

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my test program which I posted 2 years ago now synthesizes with 2016.2. Kudos Xilinx.
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Observer h4cks4w
Observer
3,486 Views
Registered: ‎08-16-2013

Re: accessing systemverilog interface parameters

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I can confirm the results @muzaffer saw.  However, if you pass the interface to another module, things break down again.

 

I've modified test test.  top2.sv demonstrates the issue:

interface test_if #(WIDTH = 0) (input aclk, aresetn);
logic [WIDTH:0] wide;

modport mp (
input aclk,
input aresetn,
input wide
);
endinterface

`define USE_MODPORT
`ifdef USE_MODPORT
module foo ( test_if.mp the_if );
`else
module foo ( test_if the_if );
`endif
localparam WIDTH = the_if.WIDTH;
//localparam WIDTH = 32;

always @(posedge the_if.aclk) begin:test
        reg [WIDTH:0] testvec;
        testvec <= 0;
end
endmodule

module top( input        reset,
 input        sys_clk);


test_if #(.WIDTH (32)) test_if(.aclk(sys_clk), .aresetn(reset));

foo
foo
( .the_if (test_if) );

endmodule

And test2.tcl will drive it:

create_project -in_memory -part xcvu095-ffvb2104-2-e
set_property target_language Verilog [current_project]

read_verilog -sv {
  top2.sv
}

synth_design -top top -part xcvu095-ffvb2104-2-e

quit

Using this command:

$ vivado -mode tcl -source test2.tcl

I get the following error:

INFO: [Synth 8-638] synthesizing module 'foo' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:13]
ERROR: [Synth 8-27] scoped/hierarchical type name not supported [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:13]
ERROR: [Synth 8-285] failed synthesizing module 'foo' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:13]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:26]

Which is pointing at foo's port map, but I think it's actually angry about "localparam WIDTH = the_if.WIDTH;".  You can see this by swapping that line with the hard-coded, commented-out line below it.  Also, the error message is different if you don't use a modport'ed interface (but I suspect it's actually the same problem):

INFO: [Synth 8-638] synthesizing module 'foo' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:15]
ERROR: [Synth 8-3892] undeclared type 'test_if'  [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:15]
ERROR: [Synth 8-285] failed synthesizing module 'foo' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:15]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/srv/home/tstrader/workspace/vivado_intf_params/top2.sv:26]

You can comment out "`define USE_MODPORT" to see this behavior.

 

This is all with Vivado 2017.1.

2,963 Views
Registered: ‎01-13-2010

Re: accessing systemverilog interface parameters

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@h4cks4w

 

Apparently this is known not to work :(

 

https://www.xilinx.com/support/answers/55135.html

 

Hopefully a future version will fix this.

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Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎05-23-2018

Re: accessing systemverilog interface parameters

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I think that Vivado is making a distinction between assigning to a localparam vs a parameter. In Vivado 2018.3, this code fails synthesis inconsistently

module my_module(
    intf.in my_intf
);
//...
parameter BUS_WIDTH = my_intf.BUS_WIDTH;
//...
endmodule

while this code seems to work

module my_module(
    intf.in my_intf
);
//...
localparam BUS_WIDTH = my_intf.BUS_WIDTH;
//...
endmodule

Using parameter allows other modules to perform a hierarchical access themselves and Vivado is possibly blowing up trying to interpret that, but localparam restricts access of the variable to the module itself. This fixed it for me at least!

-David

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