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Explorer
Explorer
427 Views
Registered: ‎11-01-2015

an issue about DIRECT_ENABLE

Hi All,

 

For the following Verilog code, the attribute DIRECT_ENABLE does not work. Could anyone give me a clue? Thank you.

part: UlstrScale, Vivado: 2017.4 

 

The en port still connects to the CE pin of the FF instead of in the data path.

 

library ieee;
use ieee.std_logic_1164.all;

entity direct_en is
port (
clk : in std_logic;
en : in std_logic;
din : in std_logic;
dout : out std_logic
);
attribute DIRECT_ENABLE : string;
attribute DIRECT_ENABLE of en : signal is "no";
end direct_en;

architecture archi of direct_en is
begin
process(clk)
begin
if rising_edge(clk) then
if en = '1' then
dout <= din;
end if;
end if;
end process;
end archi;

dir_en.PNG

 

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1 Reply
Voyager
Voyager
393 Views
Registered: ‎06-20-2017

Re: an issue about DIRECT_ENABLE

One of these architectures might work for you:

 

library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.FDCE; -- for component declaration
use UNISIM.vcomponents.LUT3; -- for component declaration
entity direct_en is
  port (
    iClk  : IN  std_logic;
    iEn   : IN  std_logic;
    iD    : IN  std_logic;
    oQ    : OUT std_logic
  );
end entity direct_en;

architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_PARTIAL_CONTROL of direct_en is
  signal    Q                   : std_logic := '0';
  attribute extract_enable      : string;
  attribute extract_enable of Q : signal is "NO";
begin -- architecture

  process(iClk)
    begin
      if rising_edge(iClk) then
        if iEn = '1' then
          Q <= iD;
        end if;
      end if;
  end process;
  oQ <= Q;

end architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_PARTIAL_CONTROL;

architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_MORE_CONTROL of direct_en is
  signal d_comb : std_logic;
  signal wQ     : std_logic;
begin -- architecture

  d_comb <= iD when iEn='1' else wQ;
  
  FDCE_U1 : FDCE  -- let's instantiate instead
  generic map (
     INIT            => '0', 
     IS_CLR_INVERTED => '0', 
     IS_C_INVERTED   => '0', 
     IS_D_INVERTED   => '0'  
  )
  port map (
    CE  => '1',   
    CLR => '0',
    C   => iClk,  
    D   => d_comb,    
    Q   => wQ      
  );
  oQ <= wQ;

end architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_MORE_CONTROL;

architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_TOTAL_CONTROL of direct_en is
  signal wD : std_logic;
  signal wQ : std_logic;
begin -- architecture

  LUT3_inst : LUT3 -- let's instantiate almost everything
  generic map (
     INIT => X"AC"  
  )
  port map (
     I0 => iD, 
     I1 => wQ, 
     I2 => iEn,  
     O  => wD   
  );
  
  FDCE_U1 : FDCE  
  generic map (
    INIT            => '0', 
    IS_CLR_INVERTED => '0', 
    IS_C_INVERTED   => '0', 
    IS_D_INVERTED   => '0'  
  )
  port map (
    CE  => '1',   
    CLR => '0',
    C   => iClk,  
    D   => wD,    
    Q   => wQ      
  );

  oQ <= wQ;

end architecture WHEN_SYNTHESIZERS_DO_NOT_OBEY_MY_WISHES_I_TAKE_TOTAL_CONTROL;


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