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7,215 Views
Registered: ‎03-31-2014

array addition

plz gv the code for addition of two arrays in vhdl..array contains signed integers..plz help..
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Xilinx Employee
Xilinx Employee
7,101 Views
Registered: ‎10-24-2013

Re: array addition

Hi,
Did you google before posting? Here are some references.

http://vhdlguru.blogspot.in/2010/02/arrays-and-records-in-vhdl.html

http://stackoverflow.com/questions/14060613/sum-of-array-elements-vhdl
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
7,082 Views
Registered: ‎10-24-2013

Re: array addition

Did the links given are of use to you?
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
7,053 Views
Registered: ‎10-24-2013

Re: array addition

Hi,

1.Use ROM to store array element

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_21b is
port (CLK : in std_logic;
EN : in std_logic;
ADDR : in std_logic_vector(5 downto 0);
DATA : out std_logic_vector(19 downto 0));
end rams_21b;

architecture syn of rams_21b is
type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0);
signal ROM : rom_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");

signal rdata : std_logic_vector(19 downto 0);
begin

rdata <= ROM(conv_integer(ADDR));

process (CLK)
begin
if (CLK'event and CLK = '1') then
if (EN = '1') then
DATA <= rdata;
end if;
end if;
end process;

end syn;

2. use arithemtic operation to addition



process (<input1>, <input2>)
begin
if <add_sub> = '1' then
<addsub_output> <= <input1> + <input2>;
else
<addsub_output> <= <input1> - <input2>;
end if;
end process;
Thanks,Vijay
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