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Observer
Observer
3,429 Views
Registered: ‎01-23-2017

attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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I am playing with VHDL configurations. From other posts (AR67946) I have learned that I must use a configuration specification.

 

I'm using a top-level module with a configuration specification:

 

entity t is end entity t;

architecture a of t is

  component cm is
  end component cm;

  for U_cm : cm use configuration work.conf;

begin

  U_cm : component cm;

end architecture a;

Then I have a hierarchy of modules 2 levels deep 'm' which instantiates a component for which eventually entity 'e' should be used. The component used by 'm' is declared with a single-bit input port 'x':

entity m is end entity m;
    
architecture a of m is

  component ce is
    port(x:in bit);
  end component ce;

  signal s : bit := '1';
begin

  U_ce : component ce port map(x=>s);

end architecture a;

Here is the entity 'e' which I want to use for component 'ce'. It has a generic which needs to be defined and also a single-bit input port albeit with a different name (which I intend to re-map in the configuration):

entity e is
  generic(MODE : boolean);
  port      (y : in bit);
end entity e;

architecture a of e is
begin
end architecture a;

Now enters the configuration for 't' where I define which entities to use for the  'cm' and 'ce' components. When configuring 'ce' I want to define the 'MODE' generic and map the 'y' port to 'x':

configuration conf of m is
for a
for U_ce : ce use entity work.e(a)
generic map(MODE=>false)
port map(y=>x)
;
end for;
end for;
end configuration conf;

However, when I try to synthesize this in vivado 2016.3 I get the error mentioned in the subject line. When I rename the port in 'e' from 'y' to 'x' and remove the port map from the configuration then synthesis passes (i.e., the generic map does work as expected). What is going wrong here?

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Visitor
Visitor
1,323 Views
Registered: ‎05-29-2018

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi!

 

I tried the folowing code (just a test) in Vivado 2018.3 and it seems to work fine:

 
configuration default_top_config of top is
    for RTL
        for U1 : generics.memory.RAM
            use entity wrappers.RAM_wrapper(default)
            generic map(
                A => 2,
                B => 3
            )
            port map(
                clk_A => clk,
                reset_A => reset
            );
        end for;
    end for;
end configuration;

For now, it looks like the issue fixed in Vivado 2018.3.

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Moderator
Moderator
3,196 Views
Registered: ‎07-21-2014

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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@strauman

 

Can you test the same with our latest 2017.2 release once as we have fixed few issues related to VHDL configuration in recent releases?

 

Thanks,

Anusheel

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Visitor
Visitor
1,444 Views
Registered: ‎05-29-2018

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi everyone.

I'm encountering the same issue in Vivado 2018.2. When I try to use VHDL configurations with generic map & port map.

When I write something like that:

configuration default_config of some_top_entity is

for some_architecture

for U1 : RAM_comp

use entity some_other_entity(some_architecture)

generic map(

some_generic => 15,    --some value

...

)

port map(

some_entity_port_name => component_port_name,           -- 'some_entity_port_name' is a different name form the one declared in the component, but with the same type and size.

....

);

end for;

end for;

end configuration;

 

I'm getting an error message "[synth 8-258] duplicate port association for 'some_entity_port' ".

When I use only the 'use' clause without the 'generic map' & 'port map' everything works fine. also when using 'use' clause and 'generic map'.

but the error appears when I'm adding the 'port map(...)'.

 

The same syntax works fine in other tools...

 

 

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Moderator
Moderator
1,420 Views
Registered: ‎03-16-2017

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi @wizedor ,

Create a fresh new thread with your query so community can help you better. Do not post your query on older thread.

Regards,
hemangd

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Observer
Observer
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Registered: ‎01-23-2017

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Why do you advise to create a new thread if this is a unresolved issue for which a thread already exists??

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Moderator
Moderator
1,377 Views
Registered: ‎03-16-2017

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi @strauman ,

Because it is an old post. I agree that unresolved but here the authors are diffrent. Hence, kindly create a new thread with your query.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer
Observer
1,359 Views
Registered: ‎01-23-2017

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Then IMHO at least the new post should link to this one and vice versa.

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Moderator
Moderator
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Registered: ‎03-16-2017

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi @strauman , 

I have checked the internal CRs and i saw that this issue has been already fixed with 2018.3. I have tried a testcase at my end as well. (As shown below.) I have also send you a testcase on your email ID.

configg.JPG

 

Regards,
hemangd

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Highlighted
Visitor
Visitor
1,324 Views
Registered: ‎05-29-2018

Re: attempt to map port in vhdl configuration declaration fails with error: [Synth 8-258] duplicate port association for 'y'

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Hi!

 

I tried the folowing code (just a test) in Vivado 2018.3 and it seems to work fine:

 
configuration default_top_config of top is
    for RTL
        for U1 : generics.memory.RAM
            use entity wrappers.RAM_wrapper(default)
            generic map(
                A => 2,
                B => 3
            )
            port map(
                clk_A => clk,
                reset_A => reset
            );
        end for;
    end for;
end configuration;

For now, it looks like the issue fixed in Vivado 2018.3.

View solution in original post