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zhongxp
Observer
Observer
5,776 Views
Registered: ‎01-30-2008

blockram utlization

hi:

 i'm using vivado and ise to synthesis the same vhdl file(xc7a200t), from the systhesis report 

vivado using more blockram then ise , the vivado auto change ram18 to ram36 , how to solve this

condition?

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5 Replies
balkris
Xilinx Employee
Xilinx Employee
5,758 Views
Registered: ‎08-01-2008

It should be fine . both ram16 and ram36 use same primitive. You are not loosing any resources here. You may share utilization report for better explanation
Thanks and Regards
Balkrishan
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anusheel
Moderator
Moderator
5,749 Views
Registered: ‎07-21-2014

@zhongxp

 

ISE and Vivado uses different synthesis engine. However, we expect better QoR from Vivado. Make sure you are looking at the right part of the synthesis log file:

Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Test | mem_reg | 16 x 512(READ_FIRST) | W | | 16 x 256(WRITE_FIRST) | | R | Port A and B | 16 | 0 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

 

Please share below details:

1. Are there any tool level switches(other than default) used in Vivado/ISE synthesis settings?

2. We would need your memory RTL file to provide root cause analysis.

3. Also, can you check the log and netlist to confirm on which part of the RTL/design is inferring more BRAMs in Vivado? 

4. Do you have several memory blocks in design hierarchies? If yes, let us know the -flatten_hierarchy setting of Vivado synthesis.

 

Thanks,
Anusheel
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zhongxp
Observer
Observer
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Registered: ‎01-30-2008

hi:

 i have found some new feature with vivado , i'm using block memory generator8.2 to generate a memory 

select1 :

true dual port ram width=16 depth=1024 

summary block resource : 18K ram 1

select2 :

true dual port ram width=32depth=512

summary block resource : 36K ram 

how to explain this condition?

 

 

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u4223374
Advisor
Advisor
5,707 Views
Registered: ‎04-26-2015

Because an 18K RAM can only produce a 32-bit wide output in simple dual-port (SDP) mode. Check UG473 for more information.

 

Since you've requested a true dual-port RAM, it's been forced to use a 36K RAM in order to get the requested port width.

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anusheel
Moderator
Moderator
5,687 Views
Registered: ‎07-21-2014

@zhongxp

 

I am agree with @u4223374. To get more information on possible configurations of TDP BRAM, check below table:

//////////////////////////////////////////////////////////////////////////
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
// ===============|===========|===========|===============|=============//
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
//////////////////////////////////////////////////////////////////////////

 

Thanks,
Anusheel
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