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Adventurer
Adventurer
492 Views
Registered: ‎01-26-2017

can $signed() be synthesized and implemented in vivado 2017.3?

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I wrote in verilog code:

 

reg signed[8:0] r_ca_out;
reg signed[11:0] buf0, buf1;

 

always@(posedge clk) buf0 <= $signed({r_ca_out, 2'b00}) + r_ca_out;

 

this is for letting buf0 = r_ca_out * 5 when r_ca_out should support signed data.

 

Dose vivado 2017.3 support it?

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Moderator
Moderator
494 Views
Registered: ‎11-04-2010

Re: can $signed() be synthesized and implemented in vivado 2017.3?

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Hi, @rggber , 

Refer to UG901, $signed() is supported.

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signed.png
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Moderator
Moderator
495 Views
Registered: ‎11-04-2010

Re: can $signed() be synthesized and implemented in vivado 2017.3?

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Hi, @rggber , 

Refer to UG901, $signed() is supported.

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signed.png
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