08-21-2018 07:23 AM
i have the following code segment in a system verilog file:
AXI_BUS #( .AXI_ADDR_WIDTH (AXI_ADDRESS_W), .AXI_DATA_WIDTH (AXI_DATA_W ), .AXI_ID_WIDTH (AXI_ID_IN ), .AXI_USER_WIDTH (AXI_USER_W ) ) axi_slave[N_SLAVE_PORT]();
apparently vivado does not like this very much. it looks like it is missing a flie in the hierarchy treeview.
how can i fix this?
08-21-2018 10:38 AM
Vivado does support SystemVerilog, but I haven't see anything similar in SystemVerilog as what you mention, the syntax is:
module_name parameters instace_identifier (port connections);
I have no data about if your ports are already declared and so you want to use implicit connection (.*);, and what exactly are you trying to do with this instruction axi_slave[N_SLAVE_PORT], by thinking axi_slave is the module identifier. If you are trying to instantiate a bunch of axi slaves, I would suggest you to use a for...generate instead.
Please check SystemVerilog LRM.
AXI_BUS #( .AXI_ADDR_WIDTH (AXI_ADDRESS_W), .AXI_DATA_WIDTH (AXI_DATA_W ), .AXI_ID_WIDTH (AXI_ID_IN ), .AXI_USER_WIDTH (AXI_USER_W ) ) axi_slave (.*);
08-21-2018 11:49 AM
Actually, I think your code should work fine with Vivado. I'm guessing "AXI_BUS" is a SystemVerilog interface. Vivado supports these.
It looks like you're trying to create an ARRAY of Interfaces(N_SLAVE_PORT) elements deep. Vivado does support arrays of interfaces too.
May I suggest changing to use a range for the interface array instead of the number of elements and see if this works? i.e.
AXI_BUS #( .AXI_ADDR_WIDTH (AXI_ADDRESS_W), .AXI_DATA_WIDTH (AXI_DATA_W ), .AXI_ID_WIDTH (AXI_ID_IN ), .AXI_USER_WIDTH (AXI_USER_W ) ) axi_slave[N_SLAVE_PORT - 1 : 0]();
We use this type of thing ALL the time (with the exact same interface parameters (slightly different parameter names, but still). It works fine in Vivado.
08-21-2018 11:52 AM - edited 08-21-2018 11:53 AM
And I disagree with the implicit connection suggestion (.*)
Those are NEVER required, and IMHO should NEVER be used. That feature of the SystemVerilog language should be gutted, burned and never thought of again... Such a bad idea.
But that's just my 2 cents.
08-22-2018 04:50 AM - edited 08-22-2018 04:59 AM
@diego73i have not found anything like this either searching the internet. i would like to avoid having to go in depth with system verilog as i would like to use the code as an ip core and not change anything in the process. usually it is easy to figure out what something does, but not in this instance.
@markcurryi will try this, thanks for the tip.
sadly neither suggestion worked.
the code should be fine though. it is the ariane cpu ( https://github.com/pulp-platform/ariane ) so i assume the problem is with vivado. i have attached a screenshot of treeview. no idea if this helps.
08-22-2018 07:19 AM
@josephg - The code you posted is fairly straightforward SystemVerilog that should be supported fine in Vivado. Can you post the exact error message that you are receiving during synthesis? That should help narrow down the issue.
08-22-2018 07:44 AM
this is the error:
[Synth 8-470] no interface 'AXI_BUS' found [Synth 8-285] failed synthesizing module 'axi_node_wrap_with_slices' ["/home/shuemer/soc/xilinx_projects/ip_core_projects/ariane/ariane.srcs/sources_1/imports/ariane/src/axi_node/axi_node_wrap_with_slices.sv":43] [Common 17-69] Command failed: Vivado Synthesis failed
08-22-2018 08:11 AM
@josephg hullo!, now that's clear ... data is very valuable. If you describe your problem as much as possible, it is faster for everyone to help and for you to have an answer.
Vivado does support SystemVerilog, and support interfaces but there are limitations in some scenarios like packaging the IP, this tools does not work with SystemVerilog interfaces at all, you need to convert those to plain ports, but I mention this only for you to know, it may be useful or not.
In the issue side, the answer is that there is no such issue :), you only miss the required files: axi_node_wrap.sv and axi_slice_wrap.sv, as soon as you add those guys, you will be ready to go. Here's the proof, I'm using old version of Vivado just to make things more clear. It should work better in 2017.x and beyond.
Pulp guys are great, but the project organization is not as good as his risc-v cores, you will need to dig into old commits to find some files.
@markcurry my dear friend, I could not agree more with you, and to be honest I mentioned implicit connection because I was as puzzled as you, but I not wanted to create more confusion to this problem. You are right, and we should tell beginners in SystemVerilog to follow some good practices as that one. Thank you for your input here.
08-23-2018 06:46 AM
08-23-2018 07:14 AM
If you want to try RISC-V, maybe you would like PicoRV32, which is formally proven, has multiple bus interfaces (simple memory, AXI, Wishbone) and is packed as Vivado IP by someone else:
The Vivado IP:
But is just a recommendation on RISC-V cores, of course you can use what is better for you.