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Adventurer
Adventurer
294 Views
Registered: ‎01-14-2008

clock constraint on internal pin

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I'm trying to create a clock constraint on an internal pin like this:

create_clock -period 50.000 -name myclk -waveform {0.000 25.000} [get_pins u1/u2/u3/myclk]

This works fine for the initial elaboration of the design but since ungrouping/flattening etc. is done by the synthesizer, halfway through synthesis the pin u1/u2/u3/myclk cannot be found anymore resulting in the clock being undefined.

How can this problem be solved? I expected that the synthesizer transforms the constraints along with any modification it makes to the netlist. But apparently this is not the case.

Thanks for any help.

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1 Solution

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Moderator
Moderator
253 Views
Registered: ‎07-21-2014

Re: clock constraint on internal pin

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@dsula

You can address this scenario by using DONT_TOUCH to make sure tool is not renaming the cells/nets. Or I would recommend to write constrains based on post-synthesis netlist instead of based on elaboration names.

Thanks
Anusheel 

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4 Replies
Moderator
Moderator
254 Views
Registered: ‎07-21-2014

Re: clock constraint on internal pin

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@dsula

You can address this scenario by using DONT_TOUCH to make sure tool is not renaming the cells/nets. Or I would recommend to write constrains based on post-synthesis netlist instead of based on elaboration names.

Thanks
Anusheel 

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Adventurer
Adventurer
240 Views
Registered: ‎01-14-2008

Re: clock constraint on internal pin

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Ok, I'll try using DONT TOUCH.

 

I'd like to avoid having to apply constraints post synthesis because things are awkward to figure out and can potentially change from one run to the next.

It would be nice if vivado were to carry constraints along and transform them insync with any code transformation it performs.

 

Cheers

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Historian
Historian
225 Views
Registered: ‎01-23-2009

Re: clock constraint on internal pin

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You haven't told us what you are trying to do here, but almost certainly it isn't recommended (or worse, is dangerous).

There is almost no condition where you should be creating a primary clock internal to the FPGA - primary clocks should ONLY be attached to ports of the design (with the exception of the TXOUTCLK and RXOUTCLK of the GTs).

If a clock is created internally, then it is always being generated by some other clock and, as such, it should be defined as a generated clock.

But more importantly, generating a clock in the fabric is not recommended. If u1/u2/u3/my_clk is a pin of a sub-module that is directly driven by a flip-flop then

  • It is still not recommended
  • It should be applied to the Q pin of the flip-flop for clarity
  • and it should be a generated clock

If it is a pin of a sub-module that comes from a LUT, then this is VERY dangerous - this can have glitches and is a construct that should not be used.

So while others have given you a way of ensuring that this clock is attached to this pin, your bigger problem is that you probably should not be doing that...

Avrum

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Adventurer
Adventurer
218 Views
Registered: ‎01-14-2008

Re: clock constraint on internal pin

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@avrumw wrote:

You haven't told us what you are trying to do here, but almost certainly it isn't recommended (or worse, is dangerous).

This is a prototype for ASIC design. It uses a shared pin. In one mode it's used as a clock going to an SPI module. In another mode it's a simple input going to a different module.

As such I want to define the signal at the SPI module as a clock, yet not the signal going to the other module, hence the need to specify an internal clock.

Maybe there's a better way (or even a right way) of doing this? I'm all open for suggestions. :-)

 

  • It is still not recommended
  • It should be applied to the Q pin of the flip-flop for clarity

Whatever works is fine for me. BUT I don't want to apply constraints to post synthesis netlists. That is cumbersome, and a general pain in the ass. The tool is hopefully smart enough to propagate the constraints from source level through synthesis to implementation. BTW synopsys tools can do that. The synthesizer writes out a new SDC file with all the transformations matched for the place'n route tool to load. Maybe Vivado can do the same, I just don't know how?

So while others have given you a way of ensuring that this clock is attached to this pin, your bigger problem is that you probably should not be doing that...


 I wish a had a choice. But unfortunately reality is different and I have to force it onto the fpga one way or the other. :-)

 

Cheers and thanks for the reply.

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