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Advisor
Advisor
3,465 Views
Registered: ‎10-10-2014

clock domain crossing and hdl naming conventions / practice

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I'm searching for good practice of naming hdl signals in a multi-clock domain situation, to clearly see from the signal name to which clock domain it belongs ( i.e. in a CDC implementation).

 

I came accross this example which I like, but I'm wondering how other people do this:

 

-- double register structure for passing a single signal into another clock domain
process (clk_a)
begin
	if rising_edge (clk_a) then
		a_reg <= signal_a
	end if;
end process;

process (clk_b)
begin
	if rising_edge (clk_b) then
		b_reg <= a_reg;
		signal_b <= b_reg;
	end if;
end process;
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Guide
Guide
6,129 Views
Registered: ‎01-23-2009

When "near" a CDC, I use the clock name as a suffix to the flip-flops.

 

So I would have

 

a_reg_clk_a - the last FF on the clk_a domain

 

a_reg_meta_clk_b - the first FF on the clk_b domain, with the word meta since it can go metastable

 

a_reg_clk_b - the synchronized version of a_reg on clk_b

 

a_reg_meta_clk_b and a_reg_clk_b should have the ASYNC_REG property set, and there would need to be a timing exception between a_reg_clk_a and [edit] a_reg_meta_clk_b.

 

Avrum

 

 

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Professor
Professor
3,440 Views
Registered: ‎08-14-2007

I always thought this was something that the tools should automate.  Some time ago I was looking to see whether any of the better language-aware editors had the option to color signal names based on the clock driving the process(es) where they get assigned.  I never found one, though.  It looks like any consistent naming convention is better than nothing, but it still allows room for error if you assign a signal name that doesn't match the signal's clock.

 

In Vivado you can use Tcl to find all registers on a particular clock, but I don't know of a way to use that to back-annotate the source signal names.  Maybe some Tcl guru will chime in with a suggestion...

-- Gabor
Highlighted
Guide
Guide
6,130 Views
Registered: ‎01-23-2009

When "near" a CDC, I use the clock name as a suffix to the flip-flops.

 

So I would have

 

a_reg_clk_a - the last FF on the clk_a domain

 

a_reg_meta_clk_b - the first FF on the clk_b domain, with the word meta since it can go metastable

 

a_reg_clk_b - the synchronized version of a_reg on clk_b

 

a_reg_meta_clk_b and a_reg_clk_b should have the ASYNC_REG property set, and there would need to be a timing exception between a_reg_clk_a and [edit] a_reg_meta_clk_b.

 

Avrum

 

 

View solution in original post

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Teacher
Teacher
3,386 Views
Registered: ‎03-31-2012

@avrumw

 

a_reg_meta_clk_b - the first FF on the clk_b domain, with the word meta since it can go metastable

 

a_reg_clk_b - the synchronized version of a_reg on clk_b

 

a_reg_meta_clk_b and a_reg_clk_b should have the ASYNC_REG property set, and there would need to be a timing exception between a_reg_clk_a and a_reg_clk_b.

 

You mean a_reg_clk_a and a_reg_meta_clk_b, here ?

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Guide
Guide
3,384 Views
Registered: ‎01-23-2009

You mean a_reg_clk_a and a_reg_meta_clk_b, here ?

 

Yes

 

Avrum