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scarlson
Visitor
Visitor
509 Views
Registered: ‎05-14-2019

confirming intermediate system verilog results (function returns, preprocessing, etc)

Hi,

 

What are the best ways to view intermediate results in a SystemVerilog file?  I am using Vivado 2019.2

 

For example - what the function $clog2() will evaluate to (or a custom func) or what a pre-processor macro will return?

 

thanks!

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2 Replies
markcurry
Scholar
Scholar
489 Views
Registered: ‎09-16-2009

Perhaps run a simulation?

Regards,

Mark

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scarlson
Visitor
Visitor
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Registered: ‎05-14-2019

 I know I can print out the returns of functions, but again that is lost in the simulation log, especially for large designs.  I was hoping for a tool to do it either in vivado or outside of.  This also doesn't seem to show the macro expansions, unless I am just enable to find them. 

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