09-15-2020 07:57 AM
What are the best ways to view intermediate results in a SystemVerilog file? I am using Vivado 2019.2
For example - what the function $clog2() will evaluate to (or a custom func) or what a pre-processor macro will return?
09-15-2020 11:33 AM
I know I can print out the returns of functions, but again that is lost in the simulation log, especially for large designs. I was hoping for a tool to do it either in vivado or outside of. This also doesn't seem to show the macro expansions, unless I am just enable to find them.