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Visitor
Visitor
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Registered: ‎02-21-2018

control_set_opt_threshold does nothing

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Hi,

I am trying to understand how the control_set_opt_threshold synthesis option affects a design. Let's consider this simple example I am using:

 

 

module top (clk, d, en, set, q);
    input clk, set, en;
    input [7:0] d;
    output reg [7:0] q;
    
    always @(posedge clk)
    begin
        if (set)
            q <= 8'hFF;
        else if (en)
            q <= d;
    end
endmodule

 

 

 

This results in a design with 8 FDSE (synchronous set, clock enable) cells. By default, synthesis should result in a single control set (since all 8 FFs will share CLK, CE, and SR).

This is a small example, but if I want to reduce the number of control sets I should be able to use the control_set_opt_threshold synthesis option.
The documentation on this option is a bit confusing. But as far as I understand, if I set the option to 16, a control set should only be created if 16
or more FFs are driven by the same CLK, CE, and SR signals. So in my example, if I set the option to 16, no control sets should be created (since only
8 FFs are driven by the same control signals) and the logic for these shared pins should instead by implemented through LUTs driving the FF D pins.

However, no matter what I set control_set_opt_threshold, the netlist (and number of control sets) created by synthesis is exactly the same.

Can someone explain what is happening here? If I am understanding the option incorrectly, please explain it. It would also be helpful if I could see a
simple example where the option makes a difference.

Thanks in advance.

 

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Voyager
Voyager
228 Views
Registered: ‎06-20-2012

Re: control_set_opt_threshold does nothing

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@dallontg 

I was referring to external inputs.

EX:

module top (clk, a,b, set, q,en);
    input clk, set, en;
    input [3:0] a,b;
    output reg [3:0] q;
    always @(posedge clk)
    begin
        if (set) begin
            q <= 4'hF;
        end
        else    begin
        if (en)
               q <= a & b;
        end 
    end
    
endmodule

Compile with synth_design -mode out_of_context -control_set_opt_threshold 16 and

synth_design -mode out_of_context -control_set_opt_threshold 0

 

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Voyager
Voyager
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Registered: ‎06-20-2012

Re: control_set_opt_threshold does nothing

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@dallontg 

"control_set_opt_threshold" is the number of fanouts necessary to move the control sets into the D logic of the register. In your example D and E are inputs so the compiler can´t do it.

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Visitor
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Registered: ‎02-21-2018

Re: control_set_opt_threshold does nothing

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Sorry, it still doesn't make sense. Of course d and en are inputs -  the FF's D and CE pins are both input pins. Additionally, the control also has a fanout of 8 (q).

Please explain further or provide an example if needed.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: control_set_opt_threshold does nothing

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Hi @dallontg ,

Have you gone through this AR#? If not please check:

https://www.xilinx.com/support/answers/58007.html

Thanks,

Raj

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Voyager
Voyager
229 Views
Registered: ‎06-20-2012

Re: control_set_opt_threshold does nothing

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@dallontg 

I was referring to external inputs.

EX:

module top (clk, a,b, set, q,en);
    input clk, set, en;
    input [3:0] a,b;
    output reg [3:0] q;
    always @(posedge clk)
    begin
        if (set) begin
            q <= 4'hF;
        end
        else    begin
        if (en)
               q <= a & b;
        end 
    end
    
endmodule

Compile with synth_design -mode out_of_context -control_set_opt_threshold 16 and

synth_design -mode out_of_context -control_set_opt_threshold 0

 

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Visitor
Visitor
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Registered: ‎02-21-2018

Re: control_set_opt_threshold does nothing

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Thanks for the detailed response. In case anyone else sees this and is wondering, my original example also works if you synthesize out of context. The key is that the inputs into the FFs in the control set can't be top-level inputs into the design. Interestingly, Vivado's report_control_sets still counts the FFs that share the CLK, CE, and R inputs as a control set even though the CE and R inputs are tied to VCC/GND. However, placement is not constrained to a single site since the logic is instead implemented through LUTs.

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